CS5346
103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux
ADC Features General Description
Multi-bit DeltaSigma Modulator
The CS5346 integrates an analog multiplexer, program-
mable gain amplifier, and stereo audio analog-to-digital
103 dB Dynamic Range
converter. The CS5346 performs stereo analog-to-digi-
-95 dB THD+N
tal (A/D) conversion of 24-bit serial values at sample
Stereo 6:1 Input Multiplexer
rates up to 192 kHz.
Programmable Gain Amplifier (PGA)
A 6:1 stereo input multiplexer is included for selecting
12 dB Gain, 0.5-dB Step Size
between line-level and microphone-level inputs. The
Zero-crossing, Click-free Transitions
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is avail-
Stereo Microphone Inputs
able for line or microphone inputs and provides
+32 dB Gain Stage
gain/attenuation of 12 dB in 0.5 dB steps.
Low-noise Bias Supply
The output of the PGA is followed by an advanced 5th-
Up to 192 kHz Sampling Rates
order, multi-bit delta-sigma modulator and digital filter-
Selectable 24-bit, Left-justified or IS Serial
ing/decimation. Sampled data is transmitted by the
Audio Interface Formats
serial audio interface at rates from 8 kHz to 192 kHz in
either Slave or Master Mode.
System Features
Integrated level translators allow easy interfacing be-
Power-down Mode
tween the CS5346 and other devices operating over a
+5 V Analog Power Supply, Nominal
wide range of logic levels.
+3.3 V Digital Power Supply, Nominal
The CS5346 is available in a 48-pin LQFP package in
Direct Interface with 3.3 V to 5 V Logic Levels Commercial (-40 to +85 C) grade. The CDB5346 Cus-
tomer Demonstration board is also available for device
Pin Compatible with CS5345 (*See Section 2
evaluation and implementation suggestions. Please re-
for details.)
fer to Ordering Information on page 38 for complete
details.
3.3 V 5 V
3.3 V to 5 V
Left PGA Output
IC /SPI
Internal Voltage
Control Data Register Configuration Right PGA Output
Reference
Interrupt
Stereo Input 1
Stereo Input 2
Overflow
Stereo Input 3
Multibit
High Pass Low-Latency
Reset
PGA
Oversampling
Filter Anti-Alias Filter
ADC
+32 dB
MUX
Stereo Input 4 /
Mic Input 1 & 2
Multibit
Serial
+32 dB
High Pass Low-Latency
Oversampling PGAA
Audio
Filter Anti-Alias Filter
ADC
Output
Stereo Input 5
Stereo Input 6
This document contains information for a product under development.
Preliminary Product Information
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2012
AUG 12
(All Rights Reserved)
CS5346
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5
2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
RECOMMENDED OPERATING CONDITIONS ................................................................................... 8
ABSOLUTE MAXIMUM RATINGS .......................................................................................................8
ANALOG CHARACTERISTICS ............................................................................................................ 9
ANALOG CHARACTERISTICS CONT. .............................................................................................. 10
DIGITAL FILTER CHARACTERISTICS .............................................................................................. 11
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 12
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 13
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 14
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ............................................ 16
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 17
4. TYPICAL CONNECTION DIAGRAM ................................................................................................... 18
5. APPLICATIONS ................................................................................................................................... 19
5.1 Recommended Power-Up Sequence .............................................................................................19
5.2 System Clocking ............................................................................................................................. 19
5.2.1 Master Clock ......................................................................................................................... 19
5.2.2 Master Mode ......................................................................................................................... 20
5.2.3 Slave Mode ........................................................................................................................... 20
5.3 High-Pass Filter and DC Offset Calibration .................................................................................... 20
5.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................21
5.5 Input Connections ........................................................................................................................... 21
5.5.1 Analog Input Configuration for 1 VRMS Input Levels ............................................................ 21
5.5.2 Analog Input Configuration for 2 VRMS Input Levels ............................................................ 22
5.6 PGA Auxiliary Analog Output ......................................................................................................... 23
5.7 Control Port Description and Timing ............................................................................................... 23
5.7.1 SPI Mode ............................................................................................................................... 23
5.7.2 IC Mode ................................................................................................................................ 24
5.8 Interrupts and Overflow .................................................................................................................. 25
5.9 Reset .............................................................................................................................................. 26
5.10 Synchronization of Multiple Devices ............................................................................................. 26
5.11 Grounding and Power Supply Decoupling .................................................................................... 26
6. REGISTER QUICK REFERENCE ........................................................................................................ 27
7. REGISTER DESCRIPTION .................................................................................................................. 28
7.1 Chip ID - Register 01h .................................................................................................................... 28
7.2 Power Control - Address 02h ......................................................................................................... 28
7.2.1 Freeze (Bit 7) ......................................................................................................................... 28
7.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 28
7.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 28
7.2.4 Power-Down Device (Bit 0) ................................................................................................... 28
7.3 ADC Control - Address 04h ............................................................................................................ 29
7.3.1 Functional Mode (Bits 7:6) .................................................................................................... 29
7.3.2 Digital Interface Format (Bit 4) .............................................................................................. 29
7.3.3 Mute (Bit 2) ............................................................................................................................ 29
7.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 29
7.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 29
7.4 MCLK Frequency - Address 05h .................................................................................................... 30
7.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 30
7.5 PGAOut Control - Address 06h ...................................................................................................... 30
7.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 30
7.6 Channel B PGA Control - Address 07h .......................................................................................... 30
2 DS861PP3