ANV22AA8A Anvo-Systems Dresden 128k x 8 nvSRAM words of 8 bits each. There are 2 separate modes of FEATURES operation: SRAM mode and non-volatile mode. In High-performance 1Mb non-volatile SRAM SRAM mode, the memory operates as an ordinary 25ns Access Time static RAM. In non-volatile operation mode, data is 10ns Output Enable Access Time transferred in parallel from SRAM to the SONOS elements (STORE) or from all of them to SRAM I = 10mA typ. at 25 ns Cycle Time CC (RECALL). In non-volatile mode SRAM functions are I = 2mA typ. at 250 ns Cycle Time CC disabled. Read Last Successful Written Address The SRAM can be read and written an unlimited number of times, while independent non-volatile data Unlimited Read/Write Endurance resides in SONOS elements. Data transfers from the Automatic non-volatile STORE on Power Down or SRAM to the SONOS elements take place Brown Out (POWERSTORE) automatically upon power down or brown out situation Non-volatile STORE under Soft Sequence or (POWERSTORE) using charge stored in a small exter- nal capacitor. Hardware (HSB) Control Transfers from the SONOS elements to the SRAM Automatic RECALL to SRAM on Power Up or after (RECALL) take place automatically on power up or Brown Out may be initiated under user control by a software Unlimited RECALL Cycles sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the non- 100k STORE Cycles volatile information is transferred into the SRAM cells. 100-Year non-volatile Data Retention STORE cycles also may be initiated under user control 3.0V to 3.6V Power Supply by a software sequence or by a single pin (HSB). Once a STORE cycle is initiated, further input or output Commercial and Industrial Temperatures are disabled until the cycle is completed. BGA48 (6x8) The PowerStore function can also be enabled or RoHS-Compliant disabled by a software sequence. With Read Last Successful Written Address it is possi- DESCRIPTION ble to read out the 3 byte of address for data where last The Anvo-Systems Dresden ANV22AA8A is a 1Mb WRITE was successful. SRAM with a non-volatile SONOS storage element included with each memory cell, organized as 128k BLOCK DIAGRAM FLASH Array 1024 x 1024 V CC STORE A7 A8 V CAP A9 A10 SRAM Array A11 A12 1024 x 1024 RECALL A13 A14 A15 STORE / A16 HSB RECALL Control DQ0 Column I/O DQ1 DQ2 Column Decoder DQ3 DQ4 DQ5 DQ6 DQ7 G A0 A1 A2 A3 A4 A5 A6 E W This product conforms to Anvo-Systems Dresden specifications Document Control Nr. 038 Rev 1.0 1 September, 2018 Input Buffer Row Decoder Software Detect Power Control A0 - A16ANV22AA8A PIN CONFIGURATION Top View 12 3 4 5 6 NC G A0 A1 A2 NC A NC NC A3 A4 E NC B DQ0 NC A5 A6 NC DQ4 C VSS DQ1 NC A7 DQ5 VCC D VCC DQ2 V A16 DQ6 VSS E CAP DQ3 NC A14 A15 NC DQ7 F NC HSB A12 A13 W NC G H NC A8 A9 A10 A11 NC PIN DESCRIPTIONS software sequence or HSB assertion and are also automatically initiated when the power supply voltage level of the chip falls below V . RECALL opera- SWITCH tions are automatically initiated upon power up and Signal Name Signal Description may also occur when the V rises above V , CC SWITCH after a low power condition. RECALL cycles may also A0 - A16 Address Inputs be initiated by a software sequence. DQ0 - DQ7 Data In/Out Chip Enable E Power up Output Enable G When the power supply is turned on from V , Chip SS Write Enable W Enable (E) has to follow the V voltage in accordance CC V Power Supply Voltage CC with the definition of V . It must not be allowed to float, IH but could be connected via a suitable pull-up resistor to V Ground SS V . CC V Capacitor Voltage CAP The Chip Enable signal (E) is edge as well as level Hardware Controlled Store/Busy HSB sensitive. This ensures that the device becomes dese- lected after Power-Down until V reaches V and CC CCmin a falling edge of E from the V level has been detected IH Device Operation thereafter. This will start the first operation. The ANV22AA8A has two separate modes of opera- Power On Reset tion: - SRAM mode and In order to prevent data corruption and inadvertent - non-volatile mode. WRITE operations during Power-up, all input signals The memory operates in SRAM mode as a standard will be ignored and Data Outputs DQ0 - DQ7 will be in fast static RAM. Data is transferred in non-volatile high impedance state. Power On Reset is exited when mode from SRAM to SONOS elements (STORE) or V reaches a stable V . Logical signals can from SONOS elements to SRAM (RECALL). In this CC CCmin applied. non-volatile mode SRAM functions are disabled. STORE cycles may be initiated under user control via a Document Control Nr. 038 Rev 1.0 Anvo-Systems Dresden September, 2018 2