EVAL-ADCMP582BCPZ

Ultrafast SiGe Voltage Comparators Data Sheet ADCMP580/ADCMP581/ADCMP582 FEATURES FUNCTIONAL BLOCK DIAGRAM V CCI 180 ps propagation delay 25 ps overdrive and slew rate dispersion V TERMINATION 8 GHz equivalent input rise time bandwidth TP V CCO 100 ps minimum pulse width V NONINVERTING P 37 ps typical output rise/fall INPUT Q OUTPUT ADCMP580/ 10 ps deterministic jitter (DJ) CML/ECL/ ADCMP581/ PECL 200 fs random jitter (RJ) ADCMP582 Q OUTPUT V INVERTING N 2 V to +3 V input range with +5 V/5 V supplies INPUT On-chip terminations at both input pins V V TERMINATION EE TN Resistor-programmable hysteresis Differential latch control LE INPUT HYS LE INPUT Power supply rejection > 70 dB V EE APPLICATIONS Figure 1. Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration GENERAL DESCRIPTION The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage The CML output stage is designed to directly drive 400 mV into comparators fabricated on the Analog Devices, Inc. proprietary 50 transmission lines terminated to ground. The NECL output XFCB3 Silicon Germanium (SiGe) bipolar process. The stages are designed to directly drive 400 mV into 50 terminated ADCMP580 features CML output drivers, the ADCMP581 to 2 V. The PECL output stages are designed to directly drive features reduced swing ECL (negative ECL) output drivers, and 400 mV into 50 terminated to V 2 V. High speed latch CCO the ADCMP582 features reduced swing PECL (positive ECL) and programmable hysteresis are also provided. The differential output drivers. latch input controls are also 50 terminated to an independent V pin to interface to either CML or ECL or to PECL logic. TT All three comparators offer 180 ps propagation delay and 100 ps minimum pulse width for 10 Gbps operation with 200 fs random The ADCMP580/ADCMP581/ADCMP582 are available in a jitter (RJ). Overdrive and slew rate dispersion are typically less 16-lead LFCSP. than 15 ps. The 5 V power supplies enable a wide 2 V to +3 V input range with logic levels referenced to the CML/NECL/PECL outputs. The inputs have 50 on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 04672-001ADCMP580/ADCMP581/ADCMP582 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 12 Applications ....................................................................................... 1 Power/Ground Layout and Bypassing ..................................... 12 Functional Block Diagram .............................................................. 1 ADCMP580/ADCMP581/ADCMP582 Family of Output Stages ............................................................................................ 12 General Description ......................................................................... 1 Using/Disabling the Latch Feature ........................................... 12 Revision History ............................................................................... 2 Optimizing High Speed Performance ..................................... 13 Specifications ..................................................................................... 3 Comparator Propagation Delay Dispersion ............................... 13 Timing Information ......................................................................... 5 Comparator Hysteresis .............................................................. 14 Absolute Maximum Ratings ............................................................ 6 Minimum Input Slew Rate Requirement ................................ 14 Thermal Considerations .............................................................. 6 Outline Dimensions ....................................................................... 15 ESD Caution .................................................................................. 6 Ordering Guide .......................................................................... 15 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 9 Typical Application Circuits .......................................................... 11 REVISION HISTORY 4/16Rev. A to Rev. B Deleted Figure 4 Renumbered Sequentially................................. 7 Changes to Figure 3 and Table 4 ..................................................... 7 Changes to Figure 4 .......................................................................... 8 Added Table 5 Renumbered Sequentially .................................... 8 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 8/07Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Table 4 ............................................................................ 7 Changes to Figure 9 .......................................................................... 8 Changes to Figure 21, Figure 22, and Figure 23 ......................... 10 Changes to Using/Disabling the Latch Feature .......................... 11 Changes to Comparator Hysteresis Section and Figure 29 ....... 13 Changes to Ordering Guide .......................................................... 14 7/05Revision 0: Initial Version Rev. B Page 2 of 16