Low Noise, 2:8 Differential Fanout Buffer Data Sheet HMC6832 FEATURES GENERAL DESCRIPTION Ultralow noise floor: 165.9 dBc/Hz or 165.2 dBc/Hz The HMC6832 is an input selectable, 2:8 differential fanout (LVPECL or LVDS) at 2000 MHz buffer designed for low noise clock distribution. The IN SEL Configurable to LVPECL or pseudo LVDS outputs control pin selects one of the two differential inputs. This input 2.5 V or 3.3 V LVPECL operation (LVDS 2.5 V only) is then buffered to all eight differential outputs. The low jitter Wideband: 10 MHz to 3500 MHz operating frequency range outputs of the HMC6832 lead to synchronized low noise Flexible input interface switching of downstream circuits, such as mixers, analog-to- LVPECL, LVDS, CML, and CMOS compatible digital converters (ADCs)/digital-to-analog converters (DACs), AC or dc coupling or serializer/deserializer (SERDES) devices. The device is capable On-chip 50 k pull-up/pull-down resistors to VDD and of low voltage, positive emitter-coupled logic (LVPECL) or low GND voltage differential signaling (LVDS) configurations by pulling Multiple output drivers the CONFIG pin low for LVPECL or high or open (internally Up to 8 differential or 16 single-ended LVPECL or LVDS pulled high) for pseudo LVDS. outputs PRODUCT HIGHLIGHTS Low speed digital control via the IN SEL and CONFIG pins 2 1. Multiple Output Configurations. 28-lead, 5 mm 5 mm, LFCSP package, 25 mm The CONFIG pin allows the user to select LVPECL or APPLICATIONS LVDS output termination. SONET, Fibre Channel, GigE clock distribution 2. Multiple Supply Voltage Operation. ADC/DAC clock distribution The HMC6832 operates at 2.5 V or 3.3 V for LVPECL Low skew and jitter clocks terminations (2.5 V only for LVDS). Wireless/wired communications 3. Low Noise. Level translation The HMC6832 noise is low, typically from 168 dBc/Hz to High performance instrumentation 162 dBc/Hz up to 3000 MHz. Medical imaging 4. Low Propagation Delay. Single-ended to differential conversions The HMC6832 displays a low delay, less than 207 ps, typical. Channel skew is also low, 5 ps, typical. 5. Low Core Current. The HMC6832 has a low core current of 56 mA, typical. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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HMC6832 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution................................................................................ 10 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ........................... 11 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 12 Product Highlights ........................................................................... 1 Test Circuits ..................................................................................... 18 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 19 Functional Block Diagram .............................................................. 3 Input Stage ................................................................................... 19 Specifications ..................................................................................... 4 LVPECL Output Stage ............................................................... 19 AC Output Characteristics .......................................................... 4 Applications Information .............................................................. 21 Output Gain and Power Characteristics ................................... 5 Recommended Solder Reflow Profile ...................................... 21 Timing Characteristics ................................................................ 8 Evaluation Printed Circuit Board (PCB) ................................ 22 Timing Specifications .................................................................. 8 Outline Dimensions ....................................................................... 23 Absolute Maximum Ratings .......................................................... 10 Ordering Guide .......................................................................... 23 Thermal Resistance .................................................................... 10 REVISION HISTORY 1/2018Rev. B to Rev. C Changes to Figure 16 Caption to Figure 18 Caption and Added Figure 24 Renumbered Sequentially .............................. 15 Figure 20 Caption ........................................................................... 14 Updated Outline Dimensions ....................................................... 23 Changes to Figure 19 and Figure 21............................................. 14 Changes to Ordering Guide .......................................................... 23 Added Figure 23 Renumbered Sequentially ...................................... 15 Changes to Figure 22 Caption and Figure 24 Caption to 9/2016Rev. A to Rev. B Figure 27 Caption ........................................................................... 15 Changes to Features Section and General Description Section . 1 Changes to Figure 28 Caption ...................................................... 16 Changes to Figure 1 .......................................................................... 3 Changes to Figure 38 Caption, Figure 40 Caption, and Figure 42 . 18 Changes to Table 1 and Table 2 ....................................................... 4 Changes to Input Stage Section and Figure 44 ........................... 19 Changes Table 3 ................................................................................ 5 Changes to Figure 45 ...................................................................... 20 Changes to Floor Density Jitter Parameter, Test Conditions/ Changes to Figure 50 Caption and Figure 51 Caption .............. 21 Comments Column Only, Table 4 and Integrated RMS Jitter, Test Conditions/Comments Column Only, Table 4..................... 6 3/2016Revision A: Initial Version Changes to Single-Sideband (SSB Phase Noise Floor) Parameter, Test Conditions/Comments Column Only, Table 5..................... 8 Changes to Figure 11 Caption and Figure 15 Caption .............. 13 Rev. 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