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ADN8102ACPZ

ADN8102ACPZ electronic component of Analog Devices

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Equalizers 3.75Gbps Quad Bidirectional

Manufacturer: Analog Devices
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25: USD 29.1093 ea
Line Total: USD 727.7325

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MOQ: 25  Multiples: 25
Pack Size: 25
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MOQ : 25
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ADN8102ACPZ
Analog Devices

25 : USD 39.5325
100 : USD 36.8066
250 : USD 35.9221

     
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3.75 Gbps Quad Bidirectional CX4 Equalizer ADN8102 FEATURES FUNCTIONAL BLOCK DIAGRAM Optimized for dc to 3.75 Gbps data LOS B ADN8102 Programmable input equalization RECEIVE TRANSMIT EQUALIZATION PRE-EMPHASIS Up to 22 dB boost at 1.875 GHz Ix B 3:0 EQ PE 2:1 Ox B 3:0 Compensates up to 30 meters of CX4 cable up to 3.75 Gbps Compensates up to 40 inches of FR4 up to 3.75 Gbps LOS A LB Programmable output pre-emphasis/de-emphasis TRANSMIT RECEIVE Up to 12 dB boost at 1.875 GHz (3.75 Gbps) PRE-EMPHASIS EQUALIZATION Compensates up to 15 meters of CX4 cable up to 3.75 Gbps Ox A 3:0 PE 2:1 EQ Ix A 3:0 Compensates up to 40 inches of FR4 up to 3.75 Gbps Flexible 1.8 V to 3.3 V core supply Per lane P/N pair inversion for routing ease EQ A 1:0 ADDR 1:0 SCL PE A 1:0 Low power: 125 mW/channel up to 3.75 Gbps EQ B 1:0 SDA CONTROL LOGIC PE B 1:0 DC- or ac-coupled differential CML inputs RESET ENA Programmable CML output levels ENB 50 on-chip termination Figure 1. Loss-of-signal detection Temperature range operation: 40C to +85C GENERAL DESCRIPTION Supports 8b10b, scrambled, or uncoded NRZ data The ADN8102 is a quad, bidirectional, CX4 cable/backplane 2 I C control interface equalizer with eight differential PECL-/CML-compatible inputs 64-lead LFCSP (QFN) package with programmable equalization and eight differential CML outputs with programmable output levels and pre-emphasis or APPLICATIONS de-emphasis. The operation of this device is optimized for NRZ 10GBase-CX4 data at rates up to 3.75 Gbps. HiGig InfiniBand The receive inputs provide programmable equalization to 1, 2 Fibre Channel compensate for up to 30 meters of CX4 cable (24 AWG) or XAUI 40 inches of FR4, and programmable pre-emphasis to compensate Gigabit Ethernet over backplane or cable for up to 15 meters of CX4 cable (24 AWG) or 40 inches of FR4 CPRI at 3.75 Gbps. Each channel also provides programmable loss-of- 50 cables signal detection and loopback capability for system testing and debugging. 2 The ADN8102 is controlled through toggle pins, an I C control interface that provides more flexible control, or a combination of both. Every channel implements an asynchronous path supporting dc to 3.75 Gbps NRZ data, fully independent of other channels. The ADN8102 has low latency and very low channel-to-channel skew. The main application for the ADN8102 is to support switching in chassis-to-chassis applications over CX4 or InfiniBand cables. The ADN8102 is packaged in a 9 mm 9 mm 64-lead LFCSP (QFN) package and operates from 40C to +85C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20082010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07060-001ADN8102 TABLE OF CONTENTS Features .............................................................................................. 1 Lane Inversion ............................................................................ 18 Applications ....................................................................................... 1 Loopback ..................................................................................... 20 Functional Block Diagram .............................................................. 1 Transmitters ................................................................................ 21 General Description ......................................................................... 1 Selective Squelch and Disable ................................................... 24 2 Revision History ............................................................................... 2 I C Control Interface ...................................................................... 25 Specif icat ions ..................................................................................... 3 Serial Interface General Functionality..................................... 25 2 Timing Specifications .................................................................. 5 I C Interface Data TransfersData Write .............................. 25 2 Absolute Maximum Ratings ............................................................ 6 I C Interface Data TransfersData Read ............................... 26 ESD Caution .................................................................................. 6 Applications Information .............................................................. 27 Pin Configuration and Function Descriptions ............................. 7 Output Compliance ................................................................... 27 Typical Performance Characteristics ............................................. 9 Printed Circuit Board (PCB) Layout Guidelines ................... 29 Theory of Operation ...................................................................... 16 Register Map ................................................................................... 31 Introduction ................................................................................ 16 Outline Dimensions ....................................................................... 33 Receivers ...................................................................................... 17 Ordering Guide .......................................................................... 33 Equalization Settings .................................................................. 17 REVISION HISTORY 10/10Rev. A to Rev. B Moved TxHeadroom and Figure 44 ............................................. 27 Changes to Power Supply/Supply Current Parameter, Table 1 ... 4 Changes to TxHeadroom and Figure 44 ..................................... 27 Added Table 20 ............................................................................... 27 Added tRESET Parameter and Note 1, Table 2 and Figure 3 Renumbered Sequentially ................................................................ 5 Added Table 21 ............................................................................... 28 Added Junction Temperature Parameter, Table 3 ........................ 6 Deleted Transmission Lines Section and Soldering Guidelines Changes to Introduction Section .................................................. 16 for Chip Scale Package Section ..................................................... 28 Added Table 5 Renumbered Sequentially .................................. 16 Changes to Printed Circuit Board (PCB) Layout Guidelines Changes to Equalization Settings Section ................................... 17 S ection .............................................................................................. 29 Added Table 7 and Advanced Equalization Settings Section ... 17 Added Figure 45, Supply Sequencing Section, Thermal Paddle Changes to Table 8 .......................................................................... 18 Design Section, and Figure 46 ...................................................... 29 Added Table 12 ............................................................................... 20 Added Stencil Design for the Thermal Paddle, Figure 47, and Changes to Loopback Section and Changes to Table 13 ........... 20 Figure 48 .......................................................................................... 30 Added Table 14 ............................................................................... 21 Changes to Table 15 ........................................................................ 21 8/08Rev. 0 to Rev. A Changes to Table 17 ........................................................................ 22 Changes to Features Section ............................................................ 1 Deleted High Current Setting and Output Level Shift Changes to Loss of Signal/Signal Detect Section ....................... 18 Section .............................................................................................. 23 Added Recommended LOS Settings Section .............................. 18 Deleted Table 14 Renumbered Sequentially .............................. 24 Deleted Figure 39 Renumbered Sequentially ............................ 18 Changes to Table 18 ........................................................................ 24 Exposed Paddle Notation Added to Outline Dimensions ........ 31 Added Table 19 ............................................................................... 24 Deleted Table 15 .............................................................................. 25 5/08Revision 0: Initial Version Added Applications Information Section and Output Compliance Section ....................................................................... 27 Rev. B Page 2 of 36

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