14-Bit, CCD Signal Processor with Precision Timing Core AD9979 FEATURES GENERAL DESCRIPTION 1.8 V analog and digital core supply voltage The AD9979 is a highly integrated CCD signal processor for Correlated double sampler (CDS) with 3 dB, 0 dB, +3 dB, and high speed digital video camera applications. Specified at pixel +6 dB gain rates of up to 65 MHz, the AD9979 consists of a complete 6 dB to 42 dB 10-bit variable gain amplifier (VGA) analog front end with analog-to-digital conversion, combined 14-bit 65 MHz analog-to-digital converter with a programmable timing driver. The Precision Timing core Black-level clamp with variable level control allows adjustment of high speed clocks with approximately Complete on-chip timing generator 240 ps resolution at 65 MHz operation. Precision Timing core with 240 ps resolution 65 MHz The analog front end includes black-level clamping, CDS, VGA, On-chip 3 V horizontal and RG drivers and a 65 MSPS, 14-bit analog-to-digital converter (ADC). The General-purpose outputs (GPOs) for shutter and system timing driver provides the high speed CCD clock drivers for RG, support HL, and H1 to H4. Operation is programmed using a 3-wire 7 mm 7 mm, 48-lead LFCSP serial interface. Internal LDO regulator circuitry Available in a space-saving, 7 mm 7 mm, 48-lead LFCSP, APPLICATIONS the AD9979 is specified over an operating temperature range of Professional HDTV camcorders 25C to +85C. Professional/high end digital cameras Broadcast cameras Industrial high speed cameras FUNCTIONAL BLOCK DIAGRAM REFT REFB AD9979 VREF CCDINP 14 DOUT D0 TO D13 CDS VGA ADC CCDINM 3dB, 0dB, +3dB, +6dB 6dB TO 42dB CLAMP LDOOUT LDO INTERNAL CLOCKS RG PRECISION HL CLI TIMING CORE 4 HORIZONTAL H1 TO H4 DRIVERS SYNC INTERNAL GENERATOR REGISTERS GPO1 GPO2 HD VD SL SCK SDI Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20072009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05957-001AD9979 TABLE OF CONTENTS Features .............................................................................................. 1 Complete FieldCombining H-Patterns ............................... 23 Applications ....................................................................................... 1 Mode Registers ........................................................................... 24 General Description ......................................................................... 1 Horizontal Timing Sequence Example .................................... 26 Functional Block Diagram .............................................................. 1 General-Purpose Outputs (GPO) ............................................ 27 Revision History ............................................................................... 2 GP Look-Up Tables (LUT) ........................................................ 30 Specif icat ions ..................................................................................... 3 Analog Front-End Description and Operation ...................... 31 Timing Specifications .................................................................. 4 Applications Information .............................................................. 35 Digital Specifications ................................................................... 5 Recommended Power-Up Sequence ....................................... 35 Analog Specifications ................................................................... 6 Standby Mode Operation .......................................................... 37 Absolute Maximum Ratings ............................................................ 7 CLI Frequency Change .............................................................. 37 Thermal Resistance ...................................................................... 7 Circuit Configuration ................................................................ 38 ESD Caution .................................................................................. 7 Grounding and Decoupling Recommendations .................... 38 Pin Configuration and Function Descriptions ............................. 8 3-Wire Serial Interface Timing ..................................................... 40 Typical Performance Characteristics ........................................... 10 Layout of Internal Registers ...................................................... 41 Equivalent Input/Output Circuits ................................................ 11 Updating of New Register Values ............................................. 42 Theory of Operation ...................................................................... 12 Complete Register Listing ......................................................... 43 Programmable Timing Generation .............................................. 13 Outline Dimensions ....................................................................... 54 Precision Timing High Speed Timing Core ............................. 13 Ordering Guide .......................................................................... 54 Horizontal Clamping and Blanking ......................................... 16 REVISION HISTORY 10/09Rev. B to Rev. C Changes to Figure 3 and Table 7 ...................................................... 8 Changes to Clock Rate (CLI) Parameter, Table 1 ......................... 3 Changes to Figure 22 ...................................................................... 16 Added GP LINE MODE Name, Table 16 ................................. 28 9/09Rev. A to Rev. B Changes to Figure 42 ...................................................................... 31 Changed SCK Falling Edge to SDATA Valid Hold Parameter to Added Example Register Settings for Power-Up Section .......... 36 SCK Rising Edge to SDATA Hold .................................................. 4 Changes to Additional Restriction Section ................................. 37 Changes to Individual HBLK Patterns Section .......................... 18 Changes to Table 22, 3 V System Compatibility Section, and Grounding and Decoupling Recommendations Section .......... 38 6/09Rev. Sp0 to Rev. A Changes to Table 33 ....................................................................... 51 Changes to Table 1 ............................................................................ 3 Changes to Table 34 ....................................................................... 52 Changes to Table 2 ............................................................................ 4 Added Exposed Paddle Notation to Outline Dimensions ........ 54 Changes to Table 3 ............................................................................ 5 Changes to Figure 2 .......................................................................... 6 2/07Revision Sp0: Initial Version Changes to Table 5 and Thermal Resistance Section ................... 7 Rev. C Page 2 of 56