Product Information

AD9643BCPZ-210

AD9643BCPZ-210 electronic component of Analog Devices

Datasheet
Analog to Digital Converters - ADC 14 Bit 210Msps Dual 1.8V

Manufacturer: Analog Devices
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1: USD 507.4173 ea
Line Total: USD 507.4173

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AD9643BCPZ-210
Analog Devices

1 : USD 305.1423
10 : USD 280.5595
25 : USD 274.371

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AD9643BCPZ-210
Analog Devices

1 : USD 163.4708
10 : USD 161.0297

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AD9643BCPZ-210
Analog Devices

1 : USD 281.1243
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Manufacturer
Product Category
RoHS - XON
Icon ROHS
Series
Mounting Style
Package / Case
Resolution
Number of Channels
Interface Type
Sampling Rate
Input Type
Architecture
Operating Supply Voltage
SNR - Signal to Noise Ratio
Minimum Operating Temperature
Maximum Operating Temperature
Packaging
Number Of Converters
Output Type
Power Consumption
Product
Type
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Reference Type
Dnl - Differential Nonlinearity
Gain Error
Inl - Integral Nonlinearity
Packagingoptionsscrubbed
Pd - Power Dissipation
Factory Pack Quantity :
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14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9643 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD SNR = 70.6 dBFS at 185 MHz A and 250 MSPS IN SFDR = 85 dBc at 185 MHz A and 250 MSPS IN VIN+A 151.6 dBFS/Hz input noise at 185 MHz, 1 dBFS A and PIPELINE IN D0 14-BIT 14 . 250 MSPS VINA ADC Total power consumption: 785 mW at 250 MSPS PARALLEL VCM AD9643 . DDR LVDS . 1.8 V supply voltages VIN+B PIPELINE AND D13 14-BIT 14 LVDS (ANSI-644 levels) outputs DRIVERS ADC VINB Integer 1-to-8 input clock divider (625 MHz maximum input) DCO Sample rates of up to 250 MSPS REFERENCE IF sampling frequencies of up to 400 MHz OR Internal ADC voltage reference 1TO 8 SERIAL PORT Flexible analog input range CLOCK OEB DIVIDER 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) PDWN ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk SCLK SDIO CSB CLK+ CLK SYNC NOTES Serial port control 1. THE D0 TO D13 PINS REPRESENT BOTH THE CHANNEL A Energy saving power-down modes AND CHANNEL B LVDS OUTPUT DATA. Figure 1. APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION The AD9643 is a dual, 14-bit analog-to-digital converter (ADC) Programming for setup and control are accomplished using a with sampling speeds of up to 250 MSPS. The AD9643 is designed 3-wire SPI-compatible serial interface. to support communications applications, where low cost, small The AD9643 is available in a 64-lead LFCSP and is specified over size, wide bandwidth, and versatility are desired. the industrial temperature range of 40C to +85C. This The dual ADC cores feature a multistage, differential pipelined product is protected by a U.S. patent. architecture with integrated output error correction logic. Each PRODUCT HIGHLIGHTS ADC features wide bandwidth inputs supporting a variety of 1. Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. user-selectable input ranges. An integrated voltage reference 2. Operation from a single 1.8 V supply and a separate digital eases design considerations. A duty cycle stabilizer is provided output driver supply accommodating LVDS outputs. to compensate for variations in the ADC clock duty cycle, 3. Proprietary differential input maintains excellent SNR allowing the converters to maintain excellent performance. performance for input frequencies of up to 400 MHz. The ADC output data is routed directly to the external, 4. SYNC input allows synchronization of multiple devices. 14-bit, LVDS output port and formatted as either interleaved or 5. 3-pin, 1.8 V SPI port for register programming and register channel multiplexed. readback. Flexible power-down options allow significant power savings, 6. Pin compatibility with the AD9613, allowing a simple when desired. migration down from 14 bits to 12 bits. This part is also pin compatible with the AD6649 and the AD6643. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09636-001AD9643 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 23 Applications ....................................................................................... 1 Voltage Reference ....................................................................... 25 Functional Block Diagram .............................................................. 1 Clock Input Considerations ...................................................... 25 General Description ......................................................................... 1 Power Dissipation and Standby Mode .................................... 26 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 27 Revision History ............................................................................... 2 ADC Overrange (OR) ................................................................ 27 Specif icat ions ..................................................................................... 3 Channel/Chip Synchronization .................................................... 28 ADC DC Specifications ............................................................... 3 Serial Port Interface (SPI) .............................................................. 29 ADC AC Specifications ............................................................... 4 Configuration Using the SPI ..................................................... 29 Digital Specifications ................................................................... 6 Hardware Interface ..................................................................... 29 Switching Specifications .............................................................. 8 SPI Accessible Features .............................................................. 30 Timing Specifications .................................................................. 9 Memory Map .................................................................................. 31 Absolute Maximum Ratings .......................................................... 11 Reading the Memory Map Register Table ............................... 31 Thermal Characteristics ............................................................ 11 Memory Map Register Table ..................................................... 32 ESD Caution ................................................................................ 11 Memory Map Register Description ......................................... 34 Pin Configurations and Function Descriptions ......................... 12 Applications Information .............................................................. 35 Typical Performance Characteristics ........................................... 16 Design Guidelines ...................................................................... 35 Equivalent Circuits ......................................................................... 22 Outline Dimensions ....................................................................... 36 Theory of Operation ...................................................................... 23 Ordering Guide .......................................................................... 36 ADC Architecture ...................................................................... 23 REVISION HISTORY 4/2019Rev. E to Rev. F 9/2011Rev. A to Rev. B Changes to General Description Section ...................................... 1 Changes to Table 1 ............................................................................. 3 Changes to Ordering Guide .......................................................... 36 Changes to Table 2, ........................................................................... 4 Changes to Table 3 ............................................................................. 6 1/2014Rev. D to Rev. E Changes to Table 4 ............................................................................. 8 Changes to Figure 32 ...................................................................... 29 Changes to Table 8 .......................................................................... 12 Changes to Table 9 .......................................................................... 14 2/2013Rev. C to Rev. D Changes to Typical Performance Characteristics Section ........ 16 Added tSSYNC and tHSYNC Minimum Parameters of 1 ns, Table 5 .. 9 Added ADC Overrange (OR) Section ......................................... 27 Changes to Channel/Chip Synchronization Section ................. 28 1/2013Rev. B to Rev. C Changes to Reading the Memory Map Register Table Changes to Features Section............................................................ 1 S ection .............................................................................................. 31 Changes to Input Referred Noise Parameter, Table 1 .................. 3 Changes to Table 14 ....................................................................... 32 Changes to Table 2 ............................................................................ 4 Changes to Memory Map Register Description Section ........... 34 Change to Table 3 ............................................................................. 6 Changes to Table 4 ............................................................................ 8 5/2011Rev. 0 to Rev. A Changes to Figure 5 ........................................................................ 14 Changes to Table 2, Worst Other (Harmonic or Spur) Changes to Figure 29 ...................................................................... 19 Max Values ......................................................................................... 4 Changes to Figure 30 ...................................................................... 20 Change to Reading the Memory Map Register Table Section ....... 31 4/2011Revision 0: Initial Version Changes to Table 14 ........................................................................ 33 Change to Memory Map Register Description Section............. 34 Updated Outline Dimensions ....................................................... 36 Rev. F Page 2 of 36

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