14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640 FEATURES FUNCTIONAL BLOCK DIAGRAM SDIO/ SCLK/ SNR = 71.8 dBc (72.8 dBFS) to 70 MHz 125 MSPS AVDD FD(0:3)A DCS DFS CSB DRVDD DVDD SFDR = 85 dBc to 70 MHz 125 MSPS Low power: 750 mW 125 MSPS FD BITS/THRESHOLD SPI DETECT SNR = 71.6 dBc (72.6 dBFS) to 70 MHz 150 MSPS D13A SFDR = 84 dBc to 70 MHz 150 MSPS PROGRAMMING DATA D0A VIN+A Low power: 820 mW 150 MSPS SHA ADC 1.8 V analog supply operation VINA SIGNAL CLK+ 1.8 V to 3.3V CMOS output supply or 1.8 V LVDS MONITOR VREF CLK output supply SENSE DIVIDE DCOA Integer 1 to 8 input clock divider 1TO 8 DCO GENERATION CML REF IF sampling frequencies to 450 MHz DCOB SELECT DUTY CYCLE Internal ADC voltage reference RBIAS D13B STABILIZER Integrated ADC sample-and-hold inputs D0B VINB Flexible analog input range: 1 V p-p to 2 V p-p SHA ADC Differential analog inputs with 650 MHz bandwidth VIN+B SIGNAL MONITOR DATA ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR Serial port control SYNC DETECT INTERFACE User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes AGND SYNC FD(0:3)B SMI SMI SMI DRGND SDFS SCLK/ SDO/ Integrated receive features PDWN OEB Fast detect/threshold bits Figure 1. Composite signal monitor PRODUCT HIGHLIGHTS APPLICATIONS 1. Integrated dual 14-bit, 80/105/125/150 MSPS ADC. Communications 2. Fast overrange detect and signal monitor with serial output. Diversity radio systems 3. Signal monitor block with dedicated serial output mode. Multimode digital receivers 4. Proprietary differential input that maintains excellent SNR GSM, EDGE, WCDMA, LTE, performance for input frequencies up to 450 MHz. CDMA2000, WiMAX, TD-SCDMA 5. Operation from a single 1.8 V supply and a separate digital I/Q demodulation systems output driver supply to accommodate 1.8 V to 3.3 V logic Smart antenna systems families. General-purpose software radios 6. A standard serial port interface that supports various Broadband data applications product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode. 7. Pin compatibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20072009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CMOS CMOS OUTPUT BUFFER OUTPUT BUFFER 06547-001AD9640 TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 28 Applications ....................................................................................... 1 Power Dissipation and Standby Mode .................................... 30 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 31 Product Highlights ........................................................................... 1 Timing ......................................................................................... 31 Revision History ............................................................................... 3 ADC Overrange and Gain Control .............................................. 32 General Description ......................................................................... 4 Fast Detect Overview ................................................................. 32 Specif icat ions ..................................................................................... 5 ADC Fast Magnitude ................................................................. 32 ADC DC SpecificationsAD9640ABCPZ-80, ADC Overrange (OR) ................................................................ 33 AD9640BCPZ-80, AD9640ABCPZ-105, and Gain Switching ............................................................................ 33 AD9640BCPZ-105 ......................................................................... 5 Signal Monitor ................................................................................ 35 ADC DC SpecificationsAD9640ABCPZ-125, Peak Detector Mode................................................................... 35 AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ-150 ......................................................................... 6 RMS/MS Magnitude Mode ......................................................... 35 ADC AC SpecificationsAD9640ABCPZ-80, Threshold Crossing Mode ......................................................... 36 AD9640BCPZ-80, AD9640ABCPZ-105, and Additional Control Bits ............................................................. 36 AD9640BCPZ-105 ......................................................................... 7 DC Correction ............................................................................ 36 ADC AC SpecificationsAD9640ABCPZ-125, Signal Monitor SPORT Output ................................................ 37 AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ 150 ......................................................................... 8 Built-In Self-Test (BIST) and Output Test .................................. 38 Digital Specifications ................................................................... 9 Built-In Self-Test (BIST) ............................................................ 38 Switching SpecificationsAD9640ABCPZ-80, Output Test Modes ..................................................................... 38 AD9640BCPZ-80, AD9640ABCPZ-105, and Channel/Chip Synchronization .................................................... 39 AD9640BCPZ-105 ..................................................................... 10 Serial Port Interface (SPI) .............................................................. 40 Switching SpecificationsAD9640ABCPZ-125, Configuration Using the SPI ..................................................... 40 AD9640BCPZ-125, AD9640ABCPZ-150, and Hardware Interface ..................................................................... 40 AD9640BCPZ-150 ..................................................................... 11 Configuration Without the SPI ................................................ 41 Timing Specifications ................................................................ 12 Absolute Maximum Ratings .......................................................... 14 SPI Accessible Features .............................................................. 41 Thermal Characteristics ............................................................ 14 Memory Map .................................................................................. 42 ESD Caution ................................................................................ 14 Reading the Memory Map Table .............................................. 42 Pin Configurations and Function Descriptions ......................... 15 External Memory Map .............................................................. 43 Memory Map Register Description ......................................... 46 Equivalent Circuits ......................................................................... 19 Applications Information .............................................................. 49 Typical Performance Characteristics ........................................... 20 Design Guidelines ...................................................................... 49 Theory of Operation ...................................................................... 25 ADC Architecture ...................................................................... 25 Outline Dimensions ....................................................................... 50 Analog Input Considerations .................................................... 25 Ordering Guide .......................................................................... 51 Voltage Reference ....................................................................... 27 Rev. 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