HDMI/DVI Buffer with Equalization
FEATURES FUNCTIONAL BLOCK DIAGRAM
1 input, 1 output HDMI/DVI link
Enables HDMI 1.3a-compliant front panel input
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables
(20 m at 2.25 Gbps)
+ 4 4 +
IN[3:0] EQ PE ON[3:0]
Fully buffered unidirectional inputs/outputs
HIGH SPEED BUFFERED
50 on-chip terminations
Low added jitter
Transmitter disable feature 2 2
Reduces power dissipation
Disables input termination
3 auxiliary buffered channels per link
Bidirectional buffered DDC lines (SDA and SCL)
LOW SPEED BUFFERED
Bidirectional buffered CEC line with integrated pull-up
resistors (27 k)
Independently powered from 5 V of HDMI input
Logic level translation (3.3 V, 5 V)
Input/output capacitance isolation TYPICAL APPLICATION
Standards compatible: HDMI, DVI, HDCP, DDC, CEC
40-lead LFCSP_VQ package (6 mm 6 mm)
Front panel buffer for advanced television (HDTV) sets
BACK PANEL FRONT PANEL
The AD8195 is an HDMI/DVI buffer featuring equalized TMDS
Figure 2. Typical AD8195 Application for HDTV Sets
inputs and preemphasized TMDS outputs, ideal for systems with
long cable runs. The AD8195 includes bidirectional buffering
for the DDC bus and bidirectional buffering with integrated
pull-up resistors for the CEC bus. The DDC and CEC buffers
1. Enables a fully HDMI 1.3a-compliant front panel input.
are powered independently of the TMDS buffers so that DDC/
2. Supports data rates of up to 2.25 Gbps, enabling 1080p deep
CEC functionality can be maintained when the system is powered
color (12-bit color) HDMI formats and greater than UXGA
off. The AD8195 meets all the requirements for sink tests as
(1600 1200) DVI resolutions.
defined in Section 8 of the HDMI Compliance Test 1.3c.
3. Input cable equalizer enables use of long cables; more than
The AD8195 is specified to operate over the 40C to +85C
20 meters (24 AWG) at data rates of up to 2.25 Gbps.
4. Auxiliary buffer isolates and buffers the DDC bus and CEC
line for a single chip, fully HDMI 1.3a-compliant solution.
5. Auxiliary buffer is powered independently from the TMDS
link so that DDC/CEC functionality can be maintained
when the system is powered off.
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Last Content Update: 02/23/2017
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AD8195: HDMI/DVI Buffer with Equalization Data Sheet
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