Low Cost SamplePort 16-Bit Stereo Asynchronous a Sample Rate Converter AD1893 SYSTEM DIAGRAM FEATURES Low Cost LQFP and PDIP Packages 3 V Supply Performance SpecifiedVery Low Power EXAMPLE EXAMPLE FREQUENCIES: Automatically Senses Sample FrequenciesNo FREQUENCIES: DAT 48kHz OR DAT 48kHz OR Programming Required CD 44.1kHz OR CD 44.1kHz OR BROADCAST 32kHz AD1893 BROADCAST 32kHz Rejects Sample Clock Jitter Accommodates Dynamically Changing Asynchronous OUTPUT SAMPLE CLOCK INPUT SAMPLE CLOCK Sample Clocks 8 kHz to 56 kHz Sample Clock Frequency Range INPUT SERIAL DATA OUTPUT SERIAL DATA Approximately 1:2 to 2:1 Ratio Between Sample Clocks 96 dB THD+N at 1 kHz 96 dB Dynamic Range The AD1893 uses multirate digital signal processing techniques Optimal Clock Tracking ControlSlow/Fast Settling to construct an output sample stream from the input sample Modes stream. The input word width is 4 to 16 bits for the AD1893. Linear Phase in All Modes Shorter input words are automatically zero-filled in the LSBs. Automatic Output Mute The output word width is 24 bits. The user can receive as many Flexible Four-Wire Serial Interfaces with Right-Justified of the output bits as desired. Internal arithmetic is performed Mode with 22-bit coefficients and 27-bit accumulation. The digital Power-Down Mode samples are processed with unity gain. On-Chip Oscillator The input and output control signals allow for considerable APPLICATIONS flexibility for interfacing to a variety of DSP chips, AES/EBU Consumer CD-R, DAT, DCC, MD and 8 mm Video Tape 2 receivers and transmitters and for I S compatible devices. Input Recorders Including Portables and output data can be independently right- or left- (with or Digital Audio Communication/Network Systems without a one bit clock delay) justified to the left/right clock Computer Multimedia Systems edge. In the right-justified mode, the MSB is delayed 16-bit clock periods from the left/right clock edge transition. Input and output data can also be independently justified to the word PRODUCT OVERVIEW clock rising edge. The data justification options are encoded on The AD1893 SamplePort is a fully digital, stereo Asynchronous two mode pins for both the input port and the output port. The Sample Rate Converter (ASRC) that solves sample rate interfacing bit clocks can also be independently configured for rising edge and compatibility problems in digital audio equipment. Concep- active or falling edge active operation. tually, this converter interpolates the input data up to a very high internal sample rate with a time resolution of 300 ps, then deci- The AD1893 SamplePort ASRC has on-chip digital coefficients mates down to the desired output sample rate. The AD1893 is that correspond to a highly oversampled 0 Hz to 20 kHz low- intended for 16-bit low cost, non-varispeed applications where low pass filter with a flat passband, a very narrow transition band, voltage, low power (i.e., battery-powered) operation is required. and a high degree of stopband attenuation. A subset of these Refer to the AD1890/AD1891 data sheet for other products in the filter coefficients are dynamically chosen on the basis of the SamplePort family. This device is asynchronous because the fre- filtered ratio between the input sample clock (LR I) and the quency and phase relationships between the input and output output sample clock (LR O), and these coefficients are then sample clocks (both are inputs to the AD1893 ASRC) are arbitrary used in an FIR convolver to perform the sample rate conversion. and need not be related by a simple integer ratio. There is no need Refer to the Theory of Operation section of this data sheet for a to explicitly select or program the input and output sample clock more thorough functional description. The low-pass filter has frequencies, as the AD1893 automatically senses the relationship been designed so that full 20 kHz bandwidth is maintained between the two clocks. The input and output sample clock fre- when the input and output sample clock frequencies are as low quencies can nominally range from 8 kHz to 56 kHz, and the ratio as 44.1 kHz. If the output sample rate drops below the input between them can vary from approximately 1:2 to 2:1. sample rate, the bandwidth of the input signal is automatically (continued on Page 4) SamplePort is a registered trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: AD1893SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltage +3.0 V Ambient Temperature 25 C Crystal Frequency 16 MHz Load Capacitance 100 pF All minimums and maximums tested except as noted. 1 PERFORMANCE (Guaranteed for V = +3.3 V to +5.0 V 10%) DD Min Max Units Dynamic Range (20 Hz to 20 kHz, 60 dB Input) 96 dB Total Harmonic Distortion + Noise (20 Hz to 20 kHz, Full-Scale Input, F /F Between 0.51 and 1.99) 94 dB SOUT SIN (1 kHz Full-Scale Input, F /F Between 0.7 and 1.4) 96 dB SOUT SIN (10 kHz Full-Scale Input, F /F Between 0.7 and 1.4) 95 dB SOUT SIN Interchannel Phase Deviation 0 Degrees Input and Output Sample Clock Jitter (For 1 dB Degradation in THD+N with 10 kHz Full-Scale Input, Slow-Settling Mode) 10 ns DIGITAL INPUTS (Guaranteed for V = +3.0 V to +5.0 V 10%) DD Min Max Units V 2.0 V IH V (V +3.0 V) 0.8 V IL DD V (+2.7 V V < +3.0 V) 0.7 V IL DD I V = +5.0 V, All Pins Except XTAL I 4 m A IH IH I V = +5.0 V, XTAL I Pin 6 m A IH IH I V = 0 V, All Pins Except XTAL I 4 m A IL IL I V = 0 V, XTAL I Pin 6 m A IL IL V I = 4 mA (V +3.0 V) 2.4 V OH OH DD V I = 4 mA (+2.7 V V < +3.0 V) 2.2 V OH OH DD V I = 4 mA 0.4 V OL OL 1 Input Capacitance 15 pF DIGITAL TIMING (Guaranteed for V = +3.0 V to +5.0 V 10%) See Figures 26 through 28. DD Min Max Units Crystal Period 62.5 125 ns t CRYSTAL F Crystal Frequency (1/t ) 16 MHz CRYSTAL CRYSTAL t Crystal LO Pulsewidth 20 ns PWL Crystal HI Pulsewidth 20 ns t PWH 1 F LR I Frequency with 16 MHz Crystal 10 56 kHz LRI t RESET LO Pulsewidth 125 ns RPWL RESET Setup to Crystal Falling 15 ns t RS 1 t BCLK I/O Period 120 ns BCLK 1 F BCLK I/O Frequency (l/t ) 8.33 MHz BCLK BCLK BCLK I/O LO Pulsewidth 55 ns t BPWL t BCLK I/O HI Pulsewidth 55 ns BPWH t WCLK I Setup to BCLK I 15 ns WSI WCLK O Setup to BCLK O 40 ns t WSO t LR I Setup to BCLK I 15 ns LRSI t LR O Setup to BCLK O 55 ns LRSO Data Setup to BCLK I 0 ns t DS t Data Hold from BCLK I 35 ns DH t Data Propagation Delay from BCLK O 90 ns DPD t Data Output Hold from BCLK O 15 ns DOH 2 REV. A