A43L0616BV-7F

A43L0616B 512K X 16 Bit X 2 Banks Synchronous DRAM Document Title 512K X 16 Bit X 2 Banks Synchronous DRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue May 12, 2003 Preliminary 0.1 Change AC Timing & DC Value February 27, 2006 1.0 Final version release April 6, 2006 Final 1.1 Modify order information July 19, 2006 1.2 Add 54B Pb-Free CSP package type July 5, 2007 1.3 February 15, 2008 Add part numbering scheme (February, 2008, Version 1.3) AMIC Technology, Corp. A43L0616B 512K X 16 Bit X 2 Banks Synchronous DRAM Features JEDEC standard 3.3V power supply Industrial operating temperature range: -40C to +85C LVTTL compatible with multiplexed address for U Pb-Free type for -F Dual banks / Pulse RAS Burst Read Single-bit Write operation MRS cycle with address key programs DQM for masking - CAS Latency (2,3) Auto & self refresh - Burst Length (1,2,4,8 & full page) 32ms refresh period (2K cycle) - Burst Type (Sequential & Interleave) Available in 54 Balls CSP (8mm X 8mm) and 50-pin All inputs are sampled at the positive going edge of the TSOP(II) packages system clock All Pb-free (Lead-free) products are RoHS compliant General Description The A43L0616B is 16,777,216 bits synchronous high data every clock cycle. Range of operating frequencies, rate Dynamic RAM organized as 2 X 524,288 words by 16 programmable latencies allows the same device to be useful bits, fabricated with AMICs high performance CMOS for a variety of high bandwidth, high performance memory technology. Synchronous design allows precise cycle control system applications. with the use of system clock. I/O transactions are possible on Pin Configuration 54 Balls CSP (8 mm x 8 mm) Top View 54 Ball (6X9) CSP 1 2 3 7 8 9 A VSS DQ15 VSSQ VDDQ DQ0 VDD B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS RAS WE G NC NC A9 BA NC CS H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD (February, 2008, Version 1.3) 1 AMIC Technology, Corp.