Product Information

A29L160AUV-70F

A29L160AUV-70F electronic component of Amic

Datasheet
IC, SM, FLASH, 16MB, 3V, BOTTOM BOOT

Manufacturer: Amic
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 2.0004 ea
Line Total: USD 2.0004

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 1
Multiples : 1
1 : USD 2.0004
10 : USD 1.7285
50 : USD 1.6597
100 : USD 1.6511
250 : USD 1.5995
500 : USD 1.5049

     
Manufacturer
Product Category
Brand
Flash Memory Type
Memory Size
Flash Memory Configuration
Ic Interface Type
Memory Case Style
No. Of Pins
Access Time
Supply Voltage Min
Supply Voltage Max
Operating Temperature Min
Operating Temperature Max
Product Range
Rohs Phthalates Compliant
Svhc
Logic Function Number
Memory Type
Memory Voltage Vcc
Operating Temperature Range
Sector Type
Supply Voltage Range
Termination Type
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A29L160A Series 2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory Document Title 2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory Revision History Rev. No. History Issue Date Remark 0.0 Initial issue April 1, 2005 Preliminary 0.1 Change Vcc min from 2.7V to 3.0V May 12, 2005 0.2 Add package type and part no A29L160AT(U)GB-70(I,U)(F) January 19, 2006 Delete 90 twp: 35 --> 45 Chip erase time: 35 --> 28 Word programming time: 40 --> 30 Notes 1.: 10,000 cycles --> 100,000 cycles Add -60 0.3 Delete A29L160AT(U)GB-(60,70)(I,U)(F) March 13, 2006 1.0 Final version release January 4, 2007 Final 1.1 Modify symbol L outline dimensions in TSOP 48L package November 16, 2007 (November, 2007, Version 1.1) AMIC Technology, Corp. A29L160A Series 2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory Features Single power supply operation - Embedded Program algorithm automatically writes and - Regulated voltage range: 3.0 to 3.6 volt read and write verifies data at specified addresses operations for compatibility with high performance 3.3 Typical 100,000 program/erase cycles per sector volt microprocessors 20-year data retention at 125C Access times: - Reliable operation for the life of the system - 60/70 (max.) CFI (Common Flash Interface) compliant Current: - Provides device-specific information to the system, - 9 mA typical active read current allowing host software to easily reconfigure for different - 20 mA typical program/erase current Flash devices - 200 nA typical CMOS standby Compatible with JEDEC-standards - 200 nA Automatic Sleep Mode current - Pinout and software compatible with single-power-supply Flexible sector architecture Flash memory standard - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors - Superior inadvertent write protection - 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors Polling and toggle bits Data - Any combination of sectors can be erased - Provides a software method of detecting completion of - Supports full chip erase program or erase operations - Sector protection: Ready / pin (RY / ) BUSY BY A hardware method of protecting sectors to prevent any - Provides a hardware method of detecting completion of inadvertent program or erase operations within that program or erase operations (not available on 44-pin sector. Temporary Sector Unprotect feature allows code SOP) changes in previously locked sectors Erase Suspend/Erase Resume Unlock Bypass Program Command - Suspends a sector erase operation to read data from, or - Reduces overall programming time when issuing program data to, a non-erasing sector, then resumes the multiple program command sequence erase operation Top or bottom boot block configurations available Embedded Algorithms Hardware reset pin ( ) RESET - Embedded Erase algorithm will automatically erase the - Hardware method to reset the device to reading array entire chip or any combination of designated sectors and data verify the erased sectors Package options - 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA - All Pb-free (Lead-free) products are RoHS compliant General Description The A29L160A is a 16Mbit, 3.3 volt-only Flash memory device has separate chip enable ( ), write enable ( ) CE WE organized as 2,097,152 bytes of 8 bits or 1,048,576 words of and output enable ( ) controls. OE 16 bits each. The 8 bits of data appear on I/O0 - I/O7 the 16 The device requires only a single 3.3 volt power supply for bits of data appear on I/O0~I/O15. The A29L160A is offered in both read and write functions. Internally generated and 48-ball FBGA, 44-pin SOP and 48-Pin TSOP packages. This regulated voltages are provided for the program and erase device is designed to be programmed in-system with the operations. standard system 3.3 volt VCC supply. Additional 12.0 volt The A29L160A is entirely software command set compatible VPP is not required for in-system write or erase operations. with the JEDEC single-power-supply Flash standard. However, the A29L160A can also be programmed in Commands are written to the command register using standard EPROM programmers. standard microprocessor write timings. Register contents The A29L160A has the first toggle bit, I/O6, which indicates serve as input to an internal state-machine that controls the whether an Embedded Program or Erase is in progress, or it erase and programming circuitry. Write cycles also internally is in the Erase Suspend. Besides the I/O6 toggle bit, the latch addresses and data needed for the programming and A29L160A has a second toggle bit, I/O2, to indicate whether erase operations. Reading data out of the device is similar to the addressed sector is being selected for erase. The reading from other Flash or EPROM devices. A29L160A also offers the ability to program in the Erase Device programming occurs by writing the proper program Suspend mode. The standard A29L160A offers access times command sequence. This initiates the Embedded Program of 60 and 70ns, allowing high-speed microprocessors to algorithm - an internal algorithm that automatically times the operate without wait states. To eliminate bus contention the program pulse widths and verifies proper program margin. (November, 2007, Version 1.1) 1 AMIC Technology, Corp.

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