AS6C62256-55SINTR

February 2007 AS6C62256 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue February 2007 Rev. 1.1 Revision of Supply current ISB1 page 3 Commercial temp 20 A Industrial temp 30 A March 26, 2013 Revision of Alliance Memory address March 26, 2013 Further Revision of Supply current - page 3 Rev 1.2 March 23, 2016 Commercial temp 15 A Industrial temp 30 A IdR (data-retention current) to be 20uA - page 7 March 23,2016 v1.2 Alliance Memory Inc. Page 0 of 12February 2007 AS6C62256 32K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION The AS6C62256 is a 262,144-bit low power CMOS Access time : 55ns static random access memory organized as 32,768 Low power consumption: words by 8 bits. It is fabricated using very high Operation current : performance, high reliability CMOS technology. Its 15mA (TYP.), V = 3.0V CC standby current is stable within the range of Standby current : 1 A (TYP.), VCC = 3.0V operating temperature. Wide range power supply : 2.7 ~ 5.5V The AS6C62256 is well designed for low power Fully Compatible with all Competitors 5V product application, and particularly well suited for battery Fully Compatible with all Competitors 3.3V product back-up nonvolatile memory application. All inputs and outputs TTL compatible Fully static operation The AS6C62256 operates with wide range power Tri-state output supply 2.7 ~ 5.5V Data retention voltage :1.5V (MIN.) . All products ROHS Compliant Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP 28-pin 8mm x 13.4mm sTSOP FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A14 Address Inputs Vcc Vss DQ0 DQ7 Data Inputs/Outputs CE Chip Enable Input 32Kx8 A0-A14 DECODER MEMORY ARRAY WE Write Enable Input OE Output Enable Input V Power Supply CC V Ground SS I/O DATA DQ0-DQ7 COLUMN I/O CIRCUIT CE CONTROL WE CIRCUIT OE Alliance Memory Inc. Page 1 of 12 March 23,2016 v1.2