AS6C4008-55SINTR

AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION The AS6C4008 is a 4,194,304-bit low power Access time : 55 ns CMOS static random access memory organized as Low power consumption: 524,288 words by 8 bits. It is fabricated using very Operating current : 30 mA (TYP.) high performance, high reliability CMOS technology. Standby current : 4 A (TYP.) Its standby current is stable within the range of Single 2.7V ~ 5.5V power supply operating temperature. All outputs TTL compatible Fully static operation The AS6C4008 is well designed for very low power Tri-state output system applications, and particularly well suited for Data retention voltage :1.5V (MIN.) battery back-up non-volatile memory application. All products ROHS Compliant Package : 32-pin 450 mil SOP 32-pin 600 mil P-DIP The AS6C4008 op erates from a sing le p owe r 32-pin 8mm x 20mm TSOP-I sup p ly of 2.7V~ 5.5Vand all inputs and outputs are 32-pin 8mm x 13.4mm STSOP fully TTL compatible 36-ball 6mm x 8mm TFBGA 32-pin 400 mil TSOP-II PRODUCT FAMILY Product Operating Power Dissipation Vcc Range Speed Family Temperature Standby(ISB1TYP.) Operating(Icc,TYP.) -40 ~ +85 AS6C4008 2.7 ~ 5.5V 55ns 4A(LL) 30mA FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION** SYMBOL DESCRIPTION A0 - A18 Address Inputs Vcc Vss DQ0 DQ7 Data Inputs/Outputs CE Chip Enable Inputs 512Kx8 A0-A18 DECODER MEMORY ARRAY WE Write Enable Input OE Output Enable Input V Power Supply CC V Ground SS NC No Connection I/O DATA DQ0-DQ7 COLUMN I/O CIRCUIT CE CONTROL WE CIRCUIT OE Page 1 of 14 AUG/09, v 1.4 Alliance Memory Inc AS6C4008 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM PIN CONFIGURATION A18 1 32 Vcc A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A11 1 32 OE A9 A10 2 31 A7 5 28 A13 A8 3 30 CE A13 DQ7 A6 6 27 A8 4 29 WE 5 28 DQ6 A5 7 26 A9 A17 DQ5 6 27 A15 7 26 DQ4 8 A4 25 A11 8 25 Vcc DQ3 A18 9 24 Vss A3 9 24 OE AS6C4008 A16 10 23 DQ2 A14 DQ1 11 22 A2 10 23 A10 A12 12 21 DQ0 A1 11 22 CE A7 A0 13 20 A6 14 19 A1 A0 12 21 DQ7 A5 15 18 A2 A4 16 17 A3 DQ0 13 20 DQ6 TSOP-I/STSOP DQ1 14 DQ5 19 DQ2 15 18 DQ4 Vss 16 17 DQ3 SOP/ P-DIP 1 32 A18 VCC 2 31 A16 A15 A14 3 30 A17 A12 W E 4 29 A7 A13 5 28 A6 A8 6 27 A5 A9 7 26 A4 A11 8 25 A3 AS6C4008 OE A0 A1 NC A3 A6 A8 A 9 24 DQ4 B A2 WE A4 A7 DQ0 A2 A10 10 23 DQ5 C NC A5 DQ1 A1 CE 11 22 Vss D Vcc A0 DQ7 12 21 E Vcc Vss DQ0 DQ6 F DQ6 13 20 DQ2 A18 A17 DQ1 DQ5 14 19 DQ7 OE G CE A16 A15 DQ3 DQ2 DQ4 A A10 A11 A12 A13 A14 15 18 H 9 VSS DQ3 16 17 1 2 3 4 5 6 TSOP-II TFBGA Page 2 of 14 AUG/09, v 1.4 Alliance Memory Inc