AS4C32M16D2A-25BCN

AS4C32M16D2A-25BCN 32M x 16 bit DDR2 Synchronous DRAM (SDRAM) Advanced (Rev. 1.4, Jun. /2014) Features Overview JEDEC Standard Compliant The AS4C32M16D2A-25BCN is a high-speed CMOS Double-Data-Rate-Two (DDR2), JEDEC standard 1.8V I/O (SSTL 18-compatible) synchronous dynamic random-access memory Power supplies: V & V = +1.8V 0.1V DD DDQ (SDRAM) containing 512 Mbits in a 16-bit wide data Operating temperature: TC = 0~95 I/Os. It is internally configured aas quad bank Supports JEDEC clock jitter specification DRAM, 4 banks x 8Mb addresses x 16 I/Os Fully synchronous operation The device is designed to comply with DDR2 DRAM Fast clock rate: 333/400/533MHz key features such as posted CAS with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) Differential Clock, CK & CK impedance adjustment, and On Die Termination(ODT). Bidirectional single/differential data strobe All of the control and address inputs are - DQS & DQS synchronized with a pair of externally supplied 4 internal banks for concurrent operation differential clocks. Inputs are latched at the cross point 4-bit prefetch architecture of differential clocks (CK rising and CK falling) Internal pipeline architecture All I/Os are synchronized with a pair of bidirectional Precharge & active power down strobes (DQS and DQS ) in a source synchronous fashion. The address bus is used to convey row, Programmable Mode & Extended Mode registers column, and bank address information in RAS Posted CAS additive latency (AL): 0, 1, 2, 3, 4, 5, 6 , CAS multiplexing style. Accesses begin with the WRITE latency = READ latency - 1 t CK registration of a Bank Activate command, and then it is Burst lengths: 4 or 8 followed by a Read or Write command. Read and write Burst type: Sequential / Interleave accesses to the DDR2 SDRAM are 4 or 8-bit burst DLL enable/disable oriented accesses start at a selected location and Off-Chip Driver (OCD) continue for a programmed number of locations in a programmed sequence. Operating the four memory - Impedance Adjustment banks in an interleaved fashion allows random access - Adjustable data-output drive strength operation to occur at a higher rate than is possible with On-die termination (ODT) standard DRAMs. An auto precharge function may be RoHS compliant enabled to provide a self-timed row precharge that is Auto Refresh and Self Refresh initiated at the end of the burst sequence. A sequential 8192 refresh cycles / 64ms and gapless data rate is possible depending on burst - Average refresh period length, CAS latency, and speed grade of the device. 7.8s 0 TC +85 3.9s +85 TC +95 84-ball 8x12.5x1.2mm (max) FBGA - Pb and Halogen Free Table 1. Ordering Information Part Number Clock Frequency Data Rate Power Supply Package AS4C32M16D2A-25BCN 400MHz 800Mbps/pin V 1.8V, V 1.8V FBGA DD DDQ Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Rev. 1.4 1 Jun. /2014AS4C32M16D2A-25BCN Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RCD RP AS4C32M16D2A-25BCN 400MHz 5 12.5 12.5 Figure 1. Ball Assignment (FBGA Top View) 123 789 VDD NC VSS VSSQ UDQS VDDQ A DQ14 VSSQ UDM UDQS VSSQ DQ15 B . VDDQ DQ9 VDDQ VDDQ DQ8 VDDQ C DQ12 VSSQ DQ11 DQ10 VSSQ DQ13 D VDD NC VSS VSSQ LDQS VDDQ E DQ6 VSSQ LDM LDQS VSSQ DQ7 F VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ G DQ4 VSSQ DQ3 DQ2 VSSQ DQ5 H VDDL VREF VSS VSSDL CK VDD J CKE WE RAS CK ODT K NC BA0 BA1 CAS CS L A10 A1 A2 A0 VDD M VSS A3 A5 A6 A4 N A7 A9 A11 A8 VSS P VDD A12 NC NC NC R Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Rev. 1.4 2 Jun. /2014