AT25SL128A-UUE-T

AT25SL128A 128-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support Features Single 1.7V - 2.0V Supply Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI) Compatible Supports SPI Modes 0 and 3 Supports Dual Output Read and Quad I/O Program and Read Supports QPI Program and Read 133 MHz Maximum Operating Frequency Clock-to-Output (t ) of 6 ns V1 Up tp 65 MB/s continuous data transfer rate Full Chip Erase Flexible, Optimized Erase Architecture for Code and Data Storage Applications 0.6 ms Typical Page Program (256 Bytes) Time 60 ms Typical 4-Kbyte Block Erase Time 200 ms Typical 32-Kbyte Block Erase Time 350 ms Typical 64-Kbyte Block Erase Time Hardware Controlled Locking of Status Registers via WP Pin 4 Kbit secured One-Time Programmable Security Register Hardware Write Protection Serial Flash Discoverable Parameters (SFDP) Register Flexible Programming Byte/Page Program (1 to 256 Bytes) Dual or Quad Input Byte/Page Program (1 to 256 Bytes) Erase/Program Suspend and Resume JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation 2 A Deep Power-Down Current (Typical) 10 A Standby current (Typical) 5 mA Active Read Current (Typical) Endurance: 100,000 program/erase cycles (4 KB, 32 KB or 64 KB blocks) Data Retention: 20 Years Industrial Temperature Range: -40C to +85C Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options 8-lead SOIC (208-mil) 8-pad DFN (6 x 5 x 0.6 mm) 21-ball die Ball Grid Array (dBGA - WLCSP) Die in Wafer Form DS-AT25SL128A109K02/20191. Introduction The Adesto AT25SL128A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25SL128A is ideal for data storage as well, eliminating the need for additional data storage devices. The erase block sizes of the AT25SL128A have been optimized to meet the needs of today s code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. SPI clock frequencies of up to 133 MHz are supported allowing equivalent clock rates of 266 MHz for Dual Output and 532 MHz for Quad Output when using the QPI and Fast Read Dual/Quad I/O instructions.The AT25SL128A array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the Page Program instructions. Pages can be erased 4KB Block, 32KB Block, 64KB Block or the entire chip. The devices operate on a single 1.7V to 2.0V power supply with current consumption as low as 5mA active and 2A for Deep Power Down. All devices offered in space-saving packages. The device supports JEDEC standard manufacturer and device identification with a 4K-bit Secured OTP. AT25SL128A 2 DS-AT25SL128A109K02/2019