58 XA Spartan-3A DSP Automotive FPGA Family Data Sheet DS705 (v2.0) April 18, 2011 Product Specification Summary The Xilinx Automotive (XA) Spartan-3A DSP family of Dual-range V supply simplifies 3.3V-only design CCAUX FPGAs solves the design challenges in most high-volume, Suspend and Hibernate modes reduce system power cost-sensitive, high-performance DSP automotive Multi-voltage, multi-standard SelectIO interface pins applications. The two-member family offers densities Up to 519 I/O pins or 227 differential signal pairs ranging from 1.8 to 3.4 million system gates, as shown in LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O Table 1. 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling Selectable output drive, up to 24 mA per pin Introduction QUIETIO standard reduces I/O switching noise XA devices are available in both extended-temperature Full 3.3V 10% compatibility and hot-swap compliance 622+ Mb/s data transfer rate per differential I/O Q-Grade (40C to +125C T ) and I-Grade (40C to J LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O +100C T ) and are qualified to the industry recognized J with integrated differential termination resistors AEC-Q100 standard. Enhanced Double Data Rate (DDR) support The XA Spartan-3A DSP family builds on the success of the DDR/DDR2 SDRAM support up to 266 Mb/s earlier XA Spartan-3E and XA Spartan-3 FPGA families by Fully compliant 32-bit, 33 MHz PCI technology support adding hardened DSP MACs with pre-adders, significantly Abundant, flexible logic resources increasing the throughput and performance of this low-cost Densities up to 53,712 logic cells, including optional shift family. These XA Spartan-3A DSP family enhancements, register combined with proven 90 nm process technology, deliver Efficient wide multiplexers, wide logic more functionality and bandwidth per dollar than ever Fast look-ahead carry logic before, setting the new standard in the programmable logic IEEE 1149.1/1532 JTAG programming/debug port industry. Hierarchical SelectRAM memory architecture Because of their exceptionally low cost, Up to 2,268 Kbits of fast block RAM with byte write XA Spartan-3A DSP FPGAs are ideally suited to a wide enables for processor applications range of automotive electronics applications, including Up to 373 Kbits of efficient distributed RAM infotainment, driver information, and driver assistance Registered outputs on the block RAM with operation of at least 280 MHz in the standard -4 speed grade modules. The XA Spartan-3A DSP family is a superior alternative to Eight Digital Clock Managers (DCMs) mask programmed ASICs. FPGAs avoid the high initial Clock skew elimination (delay locked loop) Frequency synthesis, multiplication, division mask set costs and lengthy development cycles, while also High-resolution phase shifting permitting design upgrades in the field with no hardware Wide frequency range (5 MHz to over 320 MHz) replacement necessary because of its inherent programmability, an impossibility with conventional ASICs Eight low-skew global clock networks, eight additional and ASSPs with their inflexible architecture. clocks per half device, plus abundant low-skew routing Configuration interface to industry-standard PROMs Features Low-cost, space-saving SPI serial Flash PROM Very low cost, high-performance DSP solution for x8 or x8/x16 parallel NOR Flash PROM high-volume, cost-conscious applications Unique Device DNA identifier for design authentication 250 MHz DSP48A slices using XtremeDSP solution Complete Xilinx ISE and WebPACK software Dedicated 18-bit by 18-bit multiplier support plus Spartan-3A DSP FPGA Starter Kit Available pipeline stages for enhanced performance of at MicroBlaze and PicoBlaze embedded processor least 250 MHz in the standard -4 speed grade cores 48-bit accumulator for multiply-accumulate (MAC) BGA packaging, Pb-free only operation Integrated adder for complex multiply or multiply-add Common footprints support easy density migration operation Integrated 18-bit pre-adder Optional cascaded Multiply or MAC Copyright 20082011 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. DS705 (v2.0) April 18, 2011 www.xilinx.com Product Specification 1XA Spartan-3A DSP Automotive FPGA Family Data Sheet Table 1: Summary of XA Spartan-3A DSP FPGA Attributes CLB Array Block Equivalent Maximum (One CLB = Four Slices) System Distributed RAM Dedicated Maximum Device Logic DCMs Differential (1) Gates RAM bits Bits Multipliers User I/O Total Total Cells I/O Pairs (1) Rows Columns CLBs Slices XA3SD1800A 1800K 37,440 88 48 4,160 16,640 260K 1512K 84 8 519 227 XA3SD3400A 3400K 53,712 104 58 5,968 23,872 373K 2268K 126 8 469 213 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. Refer to DS610, Spartan-3A DSP FPGA Family Data Sheet for a full product description, AC and DC specifications, and package pinout descriptions. Any values shown specifically in this XA Spartan-3A DSP Automotive FPGA Family data sheet override those shown in DS610. For information regarding reliability qualification, refer to RPT103, Xilinx Spartan-3A Family Automotive Qualification Report and RPT070, Spartan-3A Commercial Qualification Report. Contact your local Xilinx representative for more details on these reports. Key Feature Differences from Commercial XC Devices AEC-Q100 device qualification and full production part approval process (PPAP) documentation support available in both extended temperature I- and Q-Grades Guaranteed to meet full electrical specifications over the T = 40C to +125C temperature range (Q-Grade) J XA Spartan-3A DSP devices are available in the -4 speed grade only PCI-66 and PCI-X are not supported in the XA Spartan-3A DSP FPGA product line Platform Flash is not supported within the XA family XA Spartan-3A DSP devices are available in Pb-free packaging only MultiBoot is not supported in XA versions of this product. The XA Spartan-3A DSP device must be power cycled prior to reconfiguration. Architectural Overview The XA Spartan-3A DSP family architecture consists of five fundamental programmable functional elements: XtremeDSP DSP48A Slice provides an 18-bit x 18-bit multiplier, 18-bit pre-adder, 48-bit post-adder/accumulator, and cascade capabilities for various DSP applications. Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including several high-performance differential standards. Double Data-Rate (DDR) registers are included. Block RAM provides data storage in the form of 18-Kb dual-port blocks. Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. These elements are organized as shown in Figure 1. A dual ring of staggered IOBs surrounds a regular array of CLBs. The XA3SD1800A has four columns of DSP48A slices, and the XA3SD3400A has five columns of DSP48A slices. Each DSP48A has an associated block RAM. The DCMs are positioned in the center with two at the top and two at the bottom of the device and in the two outer columns of the four or five columns of block RAM and DSP48As. The XA Spartan-3A DSP family features a rich network of routing that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. DS705 (v2.0) April 18, 2011 www.xilinx.com Product Specification 2