ST7FMC1K4T3

ST7MC1xx/ST7MC2xx 8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI Features Memories 8K to 60K dual voltage Flash Program memo- ry or ROM with read-out protection capability, In-application programming and In-circuit pro- gramming. LQFP80 LQFP64 LQFP44 LQFP32 7x 7 384 to 1.5K RAM 14 x 14 14 x 14 10 x 10 HDFlash endurance: 100 cycles, data reten- tion: 40 years at 85C event detector Clock, reset and supply management 2 Communication interfaces Enhanced reset system SPI synchronous serial interface Enhanced low voltage supervisor (LVD) for LINSCI asynchronous serial interface main supply and auxiliary voltage detector Brushless motor control peripheral (AVD) with interrupt capability 6 high sink PWM output channels for sine- Clock sources: crystal/ceramic resonator os- wave or trapezoidal inverter control cillators and by-pass for external clock, clock Motor safety including asynchronous emer- security system. gency stop and write-once registers Four power saving modes: Halt, Active-halt, 4 analog inputs for rotor position detection Wait and Slow (sensorless/hall/tacho/encoder) Interrupt management Permanent magnet motor coprocessor includ- Nested interrupt controller ing multiplier, programmable filters, blanking 14 interrupt vectors plus TRAP and RESET windows and event counters MCES top level interrupt pin Operational amplifier and comparator for cur- 16 external interrupt lines (on 3 vectors) rent/voltage mode regulation and limitation Up to 60 I/O ports Analog peripheral up to 60 multifunctional bidirectional I/O lines 10-bit ADC with 16 input pins up to 41 alternate function lines In-circuit Debug up to 12 high sink outputs Instruction set 5 timers 8-bit data manipulation Main clock controller with: Real-time base, 63 basic instructions with illegal opcode de- Beep and clock-out capabilities tection Configurable window watchdog timer 17 main Addressing modes Two 16-bit timers with: 2 input captures, 2 out- 8 x 8 unsigned multiply instruction put compares, external clock input, PWM and True bit manipulation pulse generator modes Development tools 8-bit PWM Auto-reload timer with: 2 input cap- tures, 4 PWM outputs, output compare and Full hardware/software development package time base interrupt, external clock with Table 1. Device summary 1) ST7MC2N6 / ST7MC2S4 / ST7MC2S6 / ST7MC2S7 / ST7MC2S9 Features ST7MC1K2 / ST7MC1K4 / ST7MC2R6 / ST7MC2R7 / ST7MC2R9 / ST7MC2M9 Program memory - bytes 8K 16K 16K 32K 48K 60K RAM (stack) - bytes 384 (256) 768 (256) 768 (256) 1024 (256) 1536 (256) Watchdog, 16-bit Timer A, LINSCI , 10-bit ADC, MTC, 8-bit PWM ART, ICD Peripherals - SPI, 16-bit Timer B Operating 4.5 to 5.5V with f 8MHz CPU Supply vs. Frequency -40C to +85C -40C to -40C to +85C -40C to Temperature Range -40C to +85 C /-40C to +125C +85C -40C to +125C +125C 1) Package LQFP32 LQFP32 LQFP44 SDIP56 /LQFP64 LQFP64/44 LQFP80/64 LQFP44 Note 1: For development only. No production April 2009 Rev 13 1/309 1Table of Contents 1 INTRODUCTION 5 2 PIN DESCRIPTION 6 3 REGISTER & MEMORY MAP . 17 4 FLASH PROGRAM MEMORY 22 4.1 INTRODUCTION . 22 4.2 MAIN FEATURES 22 4.3 STRUCTURE 22 4.4 ICC INTERFACE . 23 4.5 ICP (IN-CIRCUIT PROGRAMMING) 24 4.6 IAP (IN-APPLICATION PROGRAMMING) . 24 4.7 RELATED DOCUMENTATION 24 4.8 REGISTER DESCRIPTION . 24 5 CENTRAL PROCESSING UNIT . 25 5.1 INTRODUCTION . 25 5.2 MAIN FEATURES 25 5.3 CPU REGISTERS 25 6 SUPPLY, RESET AND CLOCK MANAGEMENT 28 6.1 OSCILLATOR . 29 6.2 RESET SEQUENCE MANAGER (RSM) . 30 6.3 SYSTEM INTEGRITY MANAGEMENT (SI) 32 6.4 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC) . 37 7 INTERRUPTS . 40 7.1 INTRODUCTION . 40 7.2 MASKING AND PROCESSING FLOW 40 7.3 INTERRUPTS AND LOW POWER MODES 42 7.4 CONCURRENT & NESTED MANAGEMENT . 42 7.5 INTERRUPT REGISTER DESCRIPTION 43 7.6 EXTERNAL INTERRUPTS . 45 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . 47 8 POWER SAVING MODES . 50 8.1 INTRODUCTION . 50 8.2 SLOW MODE . 50 8.3 WAIT MODE 51 8.4 ACTIVE-HALT AND HALT MODES 52 9 I/O PORTS 54 9.1 INTRODUCTION . 54 9.2 FUNCTIONAL DESCRIPTION 54 9.3 I/O PORT IMPLEMENTATION 57 9.4 LOW POWER MODES 57 9.5 INTERRUPTS . 57 309 10 ON-CHIP PERIPHERALS . 60 10.1 WINDOW WATCHDOG (WWDG) 60 2/309