Product Information

LS1088ASN7MQA

Product Image X-ON

QorlQ LS1088A 64-bit Communication Processor 8-Cortex A53 Cores 1200 MHz CPU Speed 1600 MT/s RISC 2 MB L2 Cache 780-Ball FBGA Tray
Manufacturer: NXP


Price (Ex GST)

From 156.9671

30 - Global Stock
Ships to you between
Thu. 10 Dec to Wed. 16 Dec
MOQ: 60 Multiples:
Pack Size :   1
Availability Price Quantity
30 - Global Stock


Ships to you between Thu. 10 Dec to Wed. 16 Dec
Calender

MOQ : 60
Multiples : 1
60 : $ 156.9671

Buy
         
Manufacturer
NXP
Product Category
Microprocessors - MPU
RoHS - XON
Y Icon ROHS
Series
Ls1088a
Core
Arm Cortex A53
Data Bus Width
32 bit /64 bit
Maximum Clock Frequency
1200 Mhz
Interface Type
I2c, Pcie, Qsgmii, Rgmii, Sgmii, Spi, Xfi
Operating Supply Voltage
0.9 V
Maximum Operating Temperature
+105 C
Mounting Style
Smd/Smt
Package / Case
PBGA-780
Memory Type
Ddr4
Brand
Nxp Semiconductors
Cnhts
8542319000
Hts Code
8542310001
L1 Cache Data Memory
32 Kb
L1 Cache Instruction Memory
32 Kb
L2 Cache Instruction / Data Memory
1 Mb, 1 Mb
Minimum Operating Temperature
0 C
Number Of Cores
8 Core
Product Type
Microprocessors - Mpu
Factory Pack Quantity :
60
Subcategory
Microprocessors - Mpu
Tradename
Qoriq
Watchdog Timers
Watchdog Timer
Show Stocked Products With Similar Attributes. LoadingGif
Image Description
Stock Image LS1088AXE7MQA
Microprocessors - MPU 1200/1600 XT WE
Stock : 40
Stock Image LS1088AXE7PTA
Microprocessors - MPU 1400/1800 XT WE
Stock : 60
Stock Image LS1088AXE7Q1A
Microprocessors - MPU QorIQ Layerscape, 8xA53 64-Bit ARM Arch, 1600MHz, DDR4-2100, PCIe,10GbE,W/AIOP,Crypto,-40-105C Proto
Stock : 75
Stock Image LS2088ARDB-PC
Development Boards & Kits - ARM QorIQ LS2088A Reference Design
Stock : 13
Stock Image LX2160A-RDB
Development Boards & Kits - ARM LX2160A-RDB
Stock : 18
Stock Image LTE3401HX
RF Amplifier MMIC
Stock : 4618
Stock Image LTE3401LX
RF Amplifier MMIC
Stock : 2661
Image Description
Stock Image MCIMX6U8DVM10AD
Processors - Application Specialized MCIMX6U8DVM10AD/LFBGA624///STANDARD MARKING * TRAY
Stock : 32
Stock Image STM32G071RBT6
ARM Microcontrollers - MCU 16/32-BITS MICROS
Stock : 14
Stock Image R7S721000VCFP#AA1
Microprocessors - MPU RZ/A1H 400MHz 10MB QFP256 Q2A no enc MP
Stock : 9
Stock Image MCIMX6Q5EYM10AE
Processors - Application Specialized MCIMX6Q5EYM10AE/LFBGA624///TRAY MULTIPLE DP BAKEAB
Stock : 60
Stock Image FS32K146HAT0MLQT
ARM Microcontrollers - MCU FS32K146HAT0MLQT/LQFP144///TRAY MULTIPLE DP BAKEAB
Stock : 769
Stock Image S912ZVMAL3F0MLC
16-bit Microcontrollers - MCU S912ZVMAL3F0MLC/LQFP32///TRAY MULTIPLE DP BAKEABLE
Stock : 1240
Stock Image S912ZVMAL3F0WLF
16-bit Microcontrollers - MCU S912ZVMAL3F0WLF/LQFP48///TRAY MULTIPLE DP BAKEABLE
Stock : 1250
Stock Image FS32R274KSK2MMM
32-bit Microcontrollers - MCU FS32R274KSK2MMM/LFBGA257///TRAY MULTIPLE DP BAKEAB
Stock : 593
Stock Image GD32F103RCT6
GigaDevice LQFP-64_10x10x05P RoHS
Stock : 14323

Document Number LS1088A NXP Semiconductors Rev. 0, 01/2018 Data Sheet: Technical Data LS1088A QorIQ LS1088A Data Sheet Features ? Eight SerDes lanes for high-speed peripheral interfaces: ? LS1088A contains eight ARM? Cortex?-A53 (32/64 ? Three PCI Express 3.0 controllers (one supporting bit) cores with the following capabilities: x4 operation) ? Speed up to 1.6 GHz ? One serial ATA (SATA 3.0) controller supporting ? Arranged as two clusters of four cores 6 Gbps ? 32 KB L1 instruction cache (ECC protection) and 32 ? Up to two SGMII supporting 2500 Mbps KB L1 data cache (ECC protection) ? Up to four SGMII supporting 1000 Mbps ? Two 1 MB unified I/D L2 cache (ECC protection), ? Up to two XFI (10 GbE) interfaces one per Cortex-A53 core cluster ? Up to two QSGMII ? NEON? SIMD coprocessor ? Supports 1000Base-KX ? ARMv8 cryptography extensions ? Supports 10GBase-KR ? Hierarchical interconnect fabric: ? Additional peripheral interfaces include: ? Hardware-managed data coherency ? One quad serial peripheral interface (QSPI) ? Up to 700 MHz operation controller, one serial peripheral interface (SPI) ? One 32/64-bit DDR4 SDRAM memory controller: controller ? ECC and interleaving support ? Integrated flash controller (IFC) supporting NAND ? Up to 2.1 GT/s and NOR flash with 28-bit addressing and 16-bit data ? Datapath acceleration architecture 2.0 (DPAA2) ? Two USB 3.0 controllers with integrated PHY incorporates acceleration for the following functions: ? Enhanced secure digital host controller supporting ? Packet parsing, classification, and distribution SD 3.0, eMMC 4.4, and eMMC 4.5 modes (WRIOP) ? uQE supporting TDM/HDLC ? Queue management for scheduling, packet ? Four I2C controllers sequencing, and congestion management (QMan) ? Two 16550-compliant DUARTs ? Hardware buffer management for buffer allocation ? General purpose IO (GPIO), four FlexTimers, and and de-allocation (BMan) nine watchdog timers ? Cryptography acceleration (SEC) ? Trust architecture ? IEEE 1588 support ? Debug support with run control, data acquisition, ? Advanced I/O processor (AIOP) high-speed trace, and performance/event monitoring ? Parallel Ethernet interfaces: ? 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm ? Up to two RGMII interfaces pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Document Number LS1088A NXP Semiconductors Rev. 0, 01/2018 Data Sheet: Technical Data LS1088A QorIQ LS1088A Data Sheet Features ? Eight SerDes lanes for high-speed peripheral interfaces: ? LS1088A contains eight ARM? Cortex?-A53 (32/64 ? Three PCI Express 3.0 controllers (one supporting bit) cores with the following capabilities: x4 operation) ? Speed up to 1.6 GHz ? One serial ATA (SATA 3.0) controller supporting ? Arranged as two clusters of four cores 6 Gbps ? 32 KB L1 instruction cache (ECC protection) and 32 ? Up to two SGMII supporting 2500 Mbps KB L1 data cache (ECC protection) ? Up to four SGMII supporting 1000 Mbps ? Two 1 MB unified I/D L2 cache (ECC protection), ? Up to two XFI (10 GbE) interfaces one per Cortex-A53 core cluster ? Up to two QSGMII ? NEON? SIMD coprocessor ? Supports 1000Base-KX ? ARMv8 cryptography extensions ? Supports 10GBase-KR ? Hierarchical interconnect fabric: ? Additional peripheral interfaces include: ? Hardware-managed data coherency ? One quad serial peripheral interface (QSPI) ? Up to 700 MHz operation controller, one serial peripheral interface (SPI) ? One 32/64-bit DDR4 SDRAM memory controller: controller ? ECC and interleaving support ? Integrated flash controller (IFC) supporting NAND ? Up to 2.1 GT/s and NOR flash with 28-bit addressing and 16-bit data ? Datapath acceleration architecture 2.0 (DPAA2) ? Two USB 3.0 controllers with integrated PHY incorporates acceleration for the following functions: ? Enhanced secure digital host controller supporting ? Packet parsing, classification, and distribution SD 3.0, eMMC 4.4, and eMMC 4.5 modes (WRIOP) ? uQE supporting TDM/HDLC ? Queue management for scheduling, packet ? Four I2C controllers sequencing, and congestion management (QMan) ? Two 16550-compliant DUARTs ? Hardware buffer management for buffer allocation ? General purpose IO (GPIO), four FlexTimers, and and de-allocation (BMan) nine watchdog timers ? Cryptography acceleration (SEC) ? Trust architecture ? IEEE 1588 support ? Debug support with run control, data acquisition, ? Advanced I/O processor (AIOP) high-speed trace, and performance/event monitoring ? Parallel Ethernet interfaces: ? 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm ? Up to two RGMII interfaces pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Overview.............................................................................................. 3 3.17 I2C interface.............................................................................. 144 2 Pin assignments.................................................................................... 3 3.18 Integrated Flash Controller........................................................147 2.1 780 BGA ball layout diagrams..................................................4 3.19 JTAG interface.......................................................................... 166 2.2 Pinout list...................................................................................10 3.20 Quad serial peripheral interface (QuadSPI).............................. 169 3 Electrical characteristics.......................................................................51 3.21 QUICC engine specifications....................................................173 3.1 Overall DC electrical characteristics.........................................51 3.22 Serial peripheral interface (SPI)................................................ 179 3.2 General AC timing specifications............................................. 57 3.23 Universal serial bus (USB) interface.........................................182 3.3 Power sequencing......................................................................58 4 Hardware design considerations...........................................................185 3.4 Power-down requirements.........................................................61 4.1 Clock ranges.............................................................................. 185 3.5 Power characteristics.................................................................61 4.2 Power supply design..................................................................186 3.6 Power-on ramp rate................................................................... 63 5 Thermal................................................................................................ 187 3.7 Input clocks............................................................................... 63 5.1 Recommended thermal model...................................................188 3.8 RESET initialization timing specifications............................... 70 5.2 Temperature diode.....................................................................188 3.9 Battery-backed security monitor interface................................ 71 5.3 Thermal management information............................................ 188 3.10 DDR4 SDRAM controller.........................................................72 6 Package information.............................................................................191 3.11 Dual universal asynchronous receiver/transmitter (DUART) 6.1 Package parameters for the FC-PBGA......................................191 interface..................................................................................... 77 6.2 Mechanical dimensions of the FC-PBGA................................. 191 3.12 Enhanced secure digital host controller (eSDHC).....................79 7 Security fuse processor.........................................................................193 3.13 Ethernet interface (EMI, RGMII, and IEEE Std 1588).............87 8 Ordering information............................................................................193 3.14 General purpose input/output (GPIO) interface........................ 97 8.1 Part numbering nomenclature....................................................193 3.15 Generic interrupt controller (GIC) interface..............................101 8.2 Part marking ............................................................................. 194 3.16 High-speed serial interfaces (HSSI).......................................... 103 9 Revision history....................................................................................195 QorIQ LS1088A Data Sheet, Rev. 0, 01/2018 2 NXP SemiconductorsDocument Number LS1088A NXP Semiconductors Rev. 0, 01/2018 Data Sheet: Technical Data LS1088A QorIQ LS1088A Data Sheet Features ? Eight SerDes lanes for high-speed peripheral interfaces: ? LS1088A contains eight ARM? Cortex?-A53 (32/64 ? Three PCI Express 3.0 controllers (one supporting bit) cores with the following capabilities: x4 operation) ? Speed up to 1.6 GHz ? One serial ATA (SATA 3.0) controller supporting ? Arranged as two clusters of four cores 6 Gbps ? 32 KB L1 instruction cache (ECC protection) and 32 ? Up to two SGMII supporting 2500 Mbps KB L1 data cache (ECC protection) ? Up to four SGMII supporting 1000 Mbps ? Two 1 MB unified I/D L2 cache (ECC protection), ? Up to two XFI (10 GbE) interfaces one per Cortex-A53 core cluster ? Up to two QSGMII ? NEON? SIMD coprocessor ? Supports 1000Base-KX ? ARMv8 cryptography extensions ? Supports 10GBase-KR ? Hierarchical interconnect fabric: ? Additional peripheral interfaces include: ? Hardware-managed data coherency ? One quad serial peripheral interface (QSPI) ? Up to 700 MHz operation controller, one serial peripheral interface (SPI) ? One 32/64-bit DDR4 SDRAM memory controller: controller ? ECC and interleaving support ? Integrated flash controller (IFC) supporting NAND ? Up to 2.1 GT/s and NOR flash with 28-bit addressing and 16-bit data ? Datapath acceleration architecture 2.0 (DPAA2) ? Two USB 3.0 controllers with integrated PHY incorporates acceleration for the following functions: ? Enhanced secure digital host controller supporting ? Packet parsing, classification, and distribution SD 3.0, eMMC 4.4, and eMMC 4.5 modes (WRIOP) ? uQE supporting TDM/HDLC ? Queue management for scheduling, packet ? Four I2C controllers sequencing, and congestion management (QMan) ? Two 16550-compliant DUARTs ? Hardware buffer management for buffer allocation ? General purpose IO (GPIO), four FlexTimers, and and de-allocation (BMan) nine watchdog timers ? Cryptography acceleration (SEC) ? Trust architecture ? IEEE 1588 support ? Debug support with run control, data acquisition, ? Advanced I/O processor (AIOP) high-speed trace, and performance/event monitoring ? Parallel Ethernet interfaces: ? 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm ? Up to two RGMII interfaces pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Document Number LS1088A NXP Semiconductors Rev. 0, 01/2018 Data Sheet: Technical Data LS1088A QorIQ LS1088A Data Sheet Features ? Eight SerDes lanes for high-speed peripheral interfaces: ? LS1088A contains eight ARM? Cortex?-A53 (32/64 ? Three PCI Express 3.0 controllers (one supporting bit) cores with the following capabilities: x4 operation) ? Speed up to 1.6 GHz ? One serial ATA (SATA 3.0) controller supporting ? Arranged as two clusters of four cores 6 Gbps ? 32 KB L1 instruction cache (ECC protection) and 32 ? Up to two SGMII supporting 2500 Mbps KB L1 data cache (ECC protection) ? Up to four SGMII supporting 1000 Mbps ? Two 1 MB unified I/D L2 cache (ECC protection), ? Up to two XFI (10 GbE) interfaces one per Cortex-A53 core cluster ? Up to two QSGMII ? NEON? SIMD coprocessor ? Supports 1000Base-KX ? ARMv8 cryptography extensions ? Supports 10GBase-KR ? Hierarchical interconnect fabric: ? Additional peripheral interfaces include: ? Hardware-managed data coherency ? One quad serial peripheral interface (QSPI) ? Up to 700 MHz operation controller, one serial peripheral interface (SPI) ? One 32/64-bit DDR4 SDRAM memory controller: controller ? ECC and interleaving support ? Integrated flash controller (IFC) supporting NAND ? Up to 2.1 GT/s and NOR flash with 28-bit addressing and 16-bit data ? Datapath acceleration architecture 2.0 (DPAA2) ? Two USB 3.0 controllers with integrated PHY incorporates acceleration for the following functions: ? Enhanced secure digital host controller supporting ? Packet parsing, classification, and distribution SD 3.0, eMMC 4.4, and eMMC 4.5 modes (WRIOP) ? uQE supporting TDM/HDLC ? Queue management for scheduling, packet ? Four I2C controllers sequencing, and congestion management (QMan) ? Two 16550-compliant DUARTs ? Hardware buffer management for buffer allocation ? General purpose IO (GPIO), four FlexTimers, and and de-allocation (BMan) nine watchdog timers ? Cryptography acceleration (SEC) ? Trust architecture ? IEEE 1588 support ? Debug support with run control, data acquisition, ? Advanced I/O processor (AIOP) high-speed trace, and performance/event monitoring ? Parallel Ethernet interfaces: ? 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm ? Up to two RGMII interfaces pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Overview.............................................................................................. 3 3.17 I2C interface.............................................................................. 144 2 Pin assignments.................................................................................... 3 3.18 Integrated Flash Controller........................................................147 2.1 780 BGA ball layout diagrams..................................................4 3.19 JTAG interface.......................................................................... 166 2.2 Pinout list...................................................................................10 3.20 Quad serial peripheral interface (QuadSPI).............................. 169 3 Electrical characteristics.......................................................................51 3.21 QUICC engine specifications....................................................173 3.1 Overall DC electrical characteristics.........................................51 3.22 Serial peripheral interface (SPI)................................................ 179 3.2 General AC timing specifications............................................. 57 3.23 Universal serial bus (USB) interface.........................................182 3.3 Power sequencing......................................................................58 4 Hardware design considerations...........................................................185 3.4 Power-down requirements.........................................................61 4.1 Clock ranges.............................................................................. 185 3.5 Power characteristics.................................................................61 4.2 Power supply design..................................................................186 3.6 Power-on ramp rate................................................................... 63 5 Thermal................................................................................................ 187 3.7 Input clocks............................................................................... 63 5.1 Recommended thermal model...................................................188 3.8 RESET initialization timing specifications............................... 70 5.2 Temperature diode.....................................................................188 3.9 Battery-backed security monitor interface................................ 71 5.3 Thermal management information............................................ 188 3.10 DDR4 SDRAM controller.........................................................72 6 Package information.............................................................................191 3.11 Dual universal asynchronous receiver/transmitter (DUART) 6.1 Package parameters for the FC-PBGA......................................191 interface..................................................................................... 77 6.2 Mechanical dimensions of the FC-PBGA................................. 191 3.12 Enhanced secure digital host controller (eSDHC).....................79 7 Security fuse processor.........................................................................193 3.13 Ethernet interface (EMI, RGMII, and IEEE Std 1588).............87 8 Ordering information............................................................................193 3.14 General purpose input/output (GPIO) interface........................ 97 8.1 Part numbering nomenclature....................................................193 3.15 Generic interrupt controller (GIC) interface..............................101 8.2 Part marking ............................................................................. 194 3.16 High-speed serial interfaces (HSSI).......................................... 103 9 Revision history....................................................................................195 QorIQ LS1088A Data Sheet, Rev. 0, 01/2018 2 NXP SemiconductorsOverview 1 Overview A member of the Layerscape (LS1) series, the LS1088A is a cost-effective, power- efficient, and highly integrated system-on-chip (SoC) device featuring eight extremely power-efficient 64-bit ARM? Cortex?-A53 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.6 GHz. The LS1088A family of devices can be used for enterprise and service provider routers, Virtual CPE, industrial communications, security appliance and military and aerospace applications. This figure shows the LS1088A block diagram. Arm? ? Arm? ? Cortex Cortex Arm Cortex- Arm Cortex- Arm Cortex- Arm Cortex- A53 64b Core A53 64b Core A53 64b Cores A53 64b Cores A53 64b CArm Cororestex- A53 64b CArm Cororestex- A53 64b Cores A53 64b Cores Arm Cortex- Arm Cortex- 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB A53 64b Cores A53 64b Cores D-Cache D-Cache 32 KB I-Cache32 KB 32 KB I-Cache32 KB D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache32 KB D-Cache I-Cache32 KB 32 KB 32 KB 64-bit I-Cache I-Cache D-Cache D-Cache DDR4 Memory Controller 1 MB L2 - Cache 1 MB L2 - Cache Secure Boot CCI-400? Coherency Fabric Trust Zone Power Management SMMUs IFC, QuadSPI, SPI Management Complex Real Time Debug WRIOP SD/SDIO/eMMC Buffer Buffering 2x DUART Watchpoint Queue / Security Cross Trigger Buffer 4x I2C, GPIO Engine Advanced Manager 1G 1G 1G 1G (SEC) IO 4x FlexTimer Perf 1G 1G 1G 1G Processor Trace Monitor (AIOP) 1/10G 1/10G 2x USB3.0 w/PHY qDMA DPAA2 Hardware 4-Lane 10 GHz SerDes 4-Lane 10 GHz SerDes Core Complex Accelerators and Memory Control Basic Peripherals, Interconnect and Debug Networking Elements Figure 1. LS1088A block diagram 2 Pin assignments NOTE: Information given in this section is preliminary and is subject to change. QorIQ LS1088A Data Sheet, Rev. 0, 01/2018 NXP Semiconductors 3 PCIe 3.0 PCIe 3.0 PCIe 3.0 SATA 3.0 uQEDocument Number LS1088A NXP Semiconductors Rev. 0, 01/2018 Data Sheet: Technical Data LS1088A QorIQ LS1088A Data Sheet Features ? Eight SerDes lanes for high-speed peripheral interfaces: ? LS1088A contains eight ARM? Cortex?-A53 (32/64 ? Three PCI Express 3.0 controllers (one supporting bit) cores with the following capabilities: x4 operation) ? Speed up to 1.6 GHz ? One serial ATA (SATA 3.0) controller supporting ? Arranged as two clusters of four cores 6 Gbps ? 32 KB L1 instruction cache (ECC protection) and 32 ? Up to two SGMII supporting 2500 Mbps KB L1 data cache (ECC protection) ? Up to four SGMII supporting 1000 Mbps ? Two 1 MB unified I/D L2 cache (ECC protection), ? Up to two XFI (10 GbE) interfaces one per Cortex-A53 core cluster ? Up to two QSGMII ? NEON? SIMD coprocessor ? Supports 1000Base-KX ? ARMv8 cryptography extensions ? Supports 10GBase-KR ? Hierarchical interconnect fabric: ? Additional peripheral interfaces include: ? Hardware-managed data coherency ? One quad serial peripheral interface (QSPI) ? Up to 700 MHz operation controller, one serial peripheral interface (SPI) ? One 32/64-bit DDR4 SDRAM memory controller: controller ? ECC and interleaving support ? Integrated flash controller (IFC) supporting NAND ? Up to 2.1 GT/s and NOR flash with 28-bit addressing and 16-bit data ? Datapath acceleration architecture 2.0 (DPAA2) ? Two USB 3.0 controllers with integrated PHY incorporates acceleration for the following functions: ? Enhanced secure digital host controller supporting ? Packet parsing, classification, and distribution SD 3.0, eMMC 4.4, and eMMC 4.5 modes (WRIOP) ? uQE supporting TDM/HDLC ? Queue management for scheduling, packet ? Four I2C controllers sequencing, and congestion management (QMan) ? Two 16550-compliant DUARTs ? Hardware buffer management for buffer allocation ? General purpose IO (GPIO), four FlexTimers, and and de-allocation (BMan) nine watchdog timers ? Cryptography acceleration (SEC) ? Trust architecture ? IEEE 1588 support ? Debug support with run control, data acquisition, ? Advanced I/O processor (AIOP) high-speed trace, and performance/event monitoring ? Parallel Ethernet interfaces: ? 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm ? Up to two RGMII interfaces pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Document Number LS1088A NXP Semiconductors Rev. 0, 01/2018 Data Sheet: Technical Data LS1088A QorIQ LS1088A Data Sheet Features ? Eight SerDes lanes for high-speed peripheral interfaces: ? LS1088A contains eight ARM? Cortex?-A53 (32/64 ? Three PCI Express 3.0 controllers (one supporting bit) cores with the following capabilities: x4 operation) ? Speed up to 1.6 GHz ? One serial ATA (SATA 3.0) controller supporting ? Arranged as two clusters of four cores 6 Gbps ? 32 KB L1 instruction cache (ECC protection) and 32 ? Up to two SGMII supporting 2500 Mbps KB L1 data cache (ECC protection) ? Up to four SGMII supporting 1000 Mbps ? Two 1 MB unified I/D L2 cache (ECC protection), ? Up to two XFI (10 GbE) interfaces one per Cortex-A53 core cluster ? Up to two QSGMII ? NEON? SIMD coprocessor ? Supports 1000Base-KX ? ARMv8 cryptography extensions ? Supports 10GBase-KR ? Hierarchical interconnect fabric: ? Additional peripheral interfaces include: ? Hardware-managed data coherency ? One quad serial peripheral interface (QSPI) ? Up to 700 MHz operation controller, one serial peripheral interface (SPI) ? One 32/64-bit DDR4 SDRAM memory controller: controller ? ECC and interleaving support ? Integrated flash controller (IFC) supporting NAND ? Up to 2.1 GT/s and NOR flash with 28-bit addressing and 16-bit data ? Datapath acceleration architecture 2.0 (DPAA2) ? Two USB 3.0 controllers with integrated PHY incorporates acceleration for the following functions: ? Enhanced secure digital host controller supporting ? Packet parsing, classification, and distribution SD 3.0, eMMC 4.4, and eMMC 4.5 modes (WRIOP) ? uQE supporting TDM/HDLC ? Queue management for scheduling, packet ? Four I2C controllers sequencing, and congestion management (QMan) ? Two 16550-compliant DUARTs ? Hardware buffer management for buffer allocation ? General purpose IO (GPIO), four FlexTimers, and and de-allocation (BMan) nine watchdog timers ? Cryptography acceleration (SEC) ? Trust architecture ? IEEE 1588 support ? Debug support with run control, data acquisition, ? Advanced I/O processor (AIOP) high-speed trace, and performance/event monitoring ? Parallel Ethernet interfaces: ? 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm ? Up to two RGMII interfaces pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Overview.............................................................................................. 3 3.17 I2C interface.............................................................................. 144 2 Pin assignments.................................................................................... 3 3.18 Integrated Flash Controller........................................................147 2.1 780 BGA ball layout diagrams..................................................4 3.19 JTAG interface.......................................................................... 166 2.2 Pinout list...................................................................................10 3.20 Quad serial peripheral interface (QuadSPI).............................. 169 3 Electrical characteristics.......................................................................51 3.21 QUICC engine specifications....................................................173 3.1 Overall DC electrical characteristics.........................................51 3.22 Serial peripheral interface (SPI)................................................ 179 3.2 General AC timing specifications............................................. 57 3.23 Universal serial bus (USB) interface.........................................182 3.3 Power sequencing......................................................................58 4 Hardware design considerations...........................................................185 3.4 Power-down requirements.........................................................61 4.1 Clock ranges.............................................................................. 185 3.5 Power characteristics.................................................................61 4.2 Power supply design..................................................................186 3.6 Power-on ramp rate................................................................... 63 5 Thermal................................................................................................ 187 3.7 Input clocks............................................................................... 63 5.1 Recommended thermal model...................................................188 3.8 RESET initialization timing specifications............................... 70 5.2 Temperature diode.....................................................................188 3.9 Battery-backed security monitor interface................................ 71 5.3 Thermal management information............................................ 188 3.10 DDR4 SDRAM controller.........................................................72 6 Package information.............................................................................191 3.11 Dual universal asynchronous receiver/transmitter (DUART) 6.1 Package parameters for the FC-PBGA......................................191 interface..................................................................................... 77 6.2 Mechanical dimensions of the FC-PBGA................................. 191 3.12 Enhanced secure digital host controller (eSDHC).....................79 7 Security fuse processor.........................................................................193 3.13 Ethernet interface (EMI, RGMII, and IEEE Std 1588).............87 8 Ordering information............................................................................193 3.14 General purpose input/output (GPIO) interface........................ 97 8.1 Part numbering nomenclature....................................................193 3.15 Generic interrupt controller (GIC) interface..............................101 8.2 Part marking ............................................................................. 194 3.16 High-speed serial interfaces (HSSI).......................................... 103 9 Revision history....................................................................................195 QorIQ LS1088A Data Sheet, Rev. 0, 01/2018 2 NXP SemiconductorsDocument Number LS1088A NXP Semiconductors Rev. 0, 01/2018 Data Sheet: Technical Data LS1088A QorIQ LS1088A Data Sheet Features ? Eight SerDes lanes for high-speed peripheral interfaces: ? LS1088A contains eight ARM? Cortex?-A53 (32/64 ? Three PCI Express 3.0 controllers (one supporting bit) cores with the following capabilities: x4 operation) ? Speed up to 1.6 GHz ? One serial ATA (SATA 3.0) controller supporting ? Arranged as two clusters of four cores 6 Gbps ? 32 KB L1 instruction cache (ECC protection) and 32 ? Up to two SGMII supporting 2500 Mbps KB L1 data cache (ECC protection) ? Up to four SGMII supporting 1000 Mbps ? Two 1 MB unified I/D L2 cache (ECC protection), ? Up to two XFI (10 GbE) interfaces one per Cortex-A53 core cluster ? Up to two QSGMII ? NEON? SIMD coprocessor ? Supports 1000Base-KX ? ARMv8 cryptography extensions ? Supports 10GBase-KR ? Hierarchical interconnect fabric: ? Additional peripheral interfaces include: ? Hardware-managed data coherency ? One quad serial peripheral interface (QSPI) ? Up to 700 MHz operation controller, one serial peripheral interface (SPI) ? One 32/64-bit DDR4 SDRAM memory controller: controller ? ECC and interleaving support ? Integrated flash controller (IFC) supporting NAND ? Up to 2.1 GT/s and NOR flash with 28-bit addressing and 16-bit data ? Datapath acceleration architecture 2.0 (DPAA2) ? Two USB 3.0 controllers with integrated PHY incorporates acceleration for the following functions: ? Enhanced secure digital host controller supporting ? Packet parsing, classification, and distribution SD 3.0, eMMC 4.4, and eMMC 4.5 modes (WRIOP) ? uQE supporting TDM/HDLC ? Queue management for scheduling, packet ? Four I2C controllers sequencing, and congestion management (QMan) ? Two 16550-compliant DUARTs ? Hardware buffer management for buffer allocation ? General purpose IO (GPIO), four FlexTimers, and and de-allocation (BMan) nine watchdog timers ? Cryptography acceleration (SEC) ? Trust architecture ? IEEE 1588 support ? Debug support with run control, data acquisition, ? Advanced I/O processor (AIOP) high-speed trace, and performance/event monitoring ? Parallel Ethernet interfaces: ? 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm ? Up to two RGMII interfaces pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Document Number LS1088A NXP Semiconductors Rev. 0, 01/2018 Data Sheet: Technical Data LS1088A QorIQ LS1088A Data Sheet Features ? Eight SerDes lanes for high-speed peripheral interfaces: ? LS1088A contains eight ARM? Cortex?-A53 (32/64 ? Three PCI Express 3.0 controllers (one supporting bit) cores with the following capabilities: x4 operation) ? Speed up to 1.6 GHz ? One serial ATA (SATA 3.0) controller supporting ? Arranged as two clusters of four cores 6 Gbps ? 32 KB L1 instruction cache (ECC protection) and 32 ? Up to two SGMII supporting 2500 Mbps KB L1 data cache (ECC protection) ? Up to four SGMII supporting 1000 Mbps ? Two 1 MB unified I/D L2 cache (ECC protection), ? Up to two XFI (10 GbE) interfaces one per Cortex-A53 core cluster ? Up to two QSGMII ? NEON? SIMD coprocessor ? Supports 1000Base-KX ? ARMv8 cryptography extensions ? Supports 10GBase-KR ? Hierarchical interconnect fabric: ? Additional peripheral interfaces include: ? Hardware-managed data coherency ? One quad serial peripheral interface (QSPI) ? Up to 700 MHz operation controller, one serial peripheral interface (SPI) ? One 32/64-bit DDR4 SDRAM memory controller: controller ? ECC and interleaving support ? Integrated flash controller (IFC) supporting NAND ? Up to 2.1 GT/s and NOR flash with 28-bit addressing and 16-bit data ? Datapath acceleration architecture 2.0 (DPAA2) ? Two USB 3.0 controllers with integrated PHY incorporates acceleration for the following functions: ? Enhanced secure digital host controller supporting ? Packet parsing, classification, and distribution SD 3.0, eMMC 4.4, and eMMC 4.5 modes (WRIOP) ? uQE supporting TDM/HDLC ? Queue management for scheduling, packet ? Four I2C controllers sequencing, and congestion management (QMan) ? Two 16550-compliant DUARTs ? Hardware buffer management for buffer allocation ? General purpose IO (GPIO), four FlexTimers, and and de-allocation (BMan) nine watchdog timers ? Cryptography acceleration (SEC) ? Trust architecture ? IEEE 1588 support ? Debug support with run control, data acquisition, ? Advanced I/O processor (AIOP) high-speed trace, and performance/event monitoring ? Parallel Ethernet interfaces: ? 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm ? Up to two RGMII interfaces pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Overview.............................................................................................. 3 3.17 I2C interface.............................................................................. 144 2 Pin assignments.................................................................................... 3 3.18 Integrated Flash Controller........................................................147 2.1 780 BGA ball layout diagrams..................................................4 3.19 JTAG interface.......................................................................... 166 2.2 Pinout list...................................................................................10 3.20 Quad serial peripheral interface (QuadSPI).............................. 169 3 Electrical characteristics.......................................................................51 3.21 QUICC engine specifications....................................................173 3.1 Overall DC electrical characteristics.........................................51 3.22 Serial peripheral interface (SPI)................................................ 179 3.2 General AC timing specifications............................................. 57 3.23 Universal serial bus (USB) interface.........................................182 3.3 Power sequencing......................................................................58 4 Hardware design considerations...........................................................185 3.4 Power-down requirements.........................................................61 4.1 Clock ranges.............................................................................. 185 3.5 Power characteristics.................................................................61 4.2 Power supply design..................................................................186 3.6 Power-on ramp rate................................................................... 63 5 Thermal................................................................................................ 187 3.7 Input clocks............................................................................... 63 5.1 Recommended thermal model...................................................188 3.8 RESET initialization timing specifications............................... 70 5.2 Temperature diode.....................................................................188 3.9 Battery-backed security monitor interface................................ 71 5.3 Thermal management information............................................ 188 3.10 DDR4 SDRAM controller.........................................................72 6 Package information.............................................................................191 3.11 Dual universal asynchronous receiver/transmitter (DUART) 6.1 Package parameters for the FC-PBGA......................................191 interface..................................................................................... 77 6.2 Mechanical dimensions of the FC-PBGA................................. 191 3.12 Enhanced secure digital host controller (eSDHC).....................79 7 Security fuse processor.........................................................................193 3.13 Ethernet interface (EMI, RGMII, and IEEE Std 1588).............87 8 Ordering information............................................................................193 3.14 General purpose input/output (GPIO) interface........................ 97 8.1 Part numbering nomenclature....................................................193 3.15 Generic interrupt controller (GIC) interface..............................101 8.2 Part marking ............................................................................. 194 3.16 High-speed serial interfaces (HSSI).......................................... 103 9 Revision history....................................................................................195 QorIQ LS1088A Data Sheet, Rev. 0, 01/2018 2 NXP SemiconductorsOverview 1 Overview A member of the Layerscape (LS1) series, the LS1088A is a cost-effective, power- efficient, and highly integrated system-on-chip (SoC) device featuring eight extremely power-efficient 64-bit ARM? Cortex?-A53 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.6 GHz. The LS1088A family of devices can be used for enterprise and service provider routers, Virtual CPE, industrial communications, security appliance and military and aerospace applications. This figure shows the LS1088A block diagram. Arm? ? Arm? ? Cortex Cortex Arm Cortex- Arm Cortex- Arm Cortex- Arm Cortex- A53 64b Core A53 64b Core A53 64b Cores A53 64b Cores A53 64b CArm Cororestex- A53 64b CArm Cororestex- A53 64b Cores A53 64b Cores Arm Cortex- Arm Cortex- 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB A53 64b Cores A53 64b Cores D-Cache D-Cache 32 KB I-Cache32 KB 32 KB I-Cache32 KB D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache32 KB D-Cache I-Cache32 KB 32 KB 32 KB 64-bit I-Cache I-Cache D-Cache D-Cache DDR4 Memory Controller 1 MB L2 - Cache 1 MB L2 - Cache Secure Boot CCI-400? Coherency Fabric Trust Zone Power Management SMMUs IFC, QuadSPI, SPI Management Complex Real Time Debug WRIOP SD/SDIO/eMMC Buffer Buffering 2x DUART Watchpoint Queue / Security Cross Trigger Buffer 4x I2C, GPIO Engine Advanced Manager 1G 1G 1G 1G (SEC) IO 4x FlexTimer Perf 1G 1G 1G 1G Processor Trace Monitor (AIOP) 1/10G 1/10G 2x USB3.0 w/PHY qDMA DPAA2 Hardware 4-Lane 10 GHz SerDes 4-Lane 10 GHz SerDes Core Complex Accelerators and Memory Control Basic Peripherals, Interconnect and Debug Networking Elements Figure 1. LS1088A block diagram 2 Pin assignments NOTE: Information given in this section is preliminary and is subject to change. QorIQ LS1088A Data Sheet, Rev. 0, 01/2018 NXP Semiconductors 3 PCIe 3.0 PCIe 3.0 PCIe 3.0 SATA 3.0 uQE

Tariff Concession Code
Tariff Desc

Free
8542.31.00 52 No ..CMOS and MOS Microprocessors (MPU), Microcontrollers (MCU) and Digital Signal Processors (DSP)

Customer Comments  

Log in or register to post comments.

Customer Reviews

No reviews yet.