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SY89829UHY TR

Product Image X-ON

Clock Drivers & Distribution
Manufacturer: Microchip


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From 9.1363

957 - Global Stock
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SY89829UHY TR
Microchip

1 : $ 10.042
10 : $ 9.4826
25 : $ 9.3228
100 : $ 9.1363

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Manufacturer
Microchip
Product Category
Clock Drivers & Distribution
RoHS - XON
Y Icon ROHS
Multiply / Divide Factor
2:10
Package / Case
TQFP-64
Packaging
Reel
Brand
Microchip Technology / Micrel
Mounting Style
Smd/Smt
Factory Pack Quantity :
1000
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? Precision Edge 2.5V/3.3V HIGH-PERFORMANCE, DUAL 1:10 Micrel, Inc. SY89829U? Precision Edge OR LVPECL CLOCK DRIVER w/ INTERNAL SY89829U TERMINATION AND REDUNDANT SWITCHOVER FEATURES Dual 1:10 fanout buffer/translator ? Precision Edge Accepts LVPECL or LVDS inputs Multiplexed inputs ideal for redundant clock DESCRIPTION switchover Guaranteed AC parameters: The SY89829U is a High Performance dual 1:10 or ? > 2GHz f (toggle) MAX single 1:20 LVPECL Clock Driver. The part is designed for ? < 50ps ch-ch skew use in low voltage (2.5V/3.3V) applications which require a LVDS input includes 100????? internal termination large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed Low supply voltage: 2.5V, 3.3V from either LVDS or LVPECL by the CLK_SEL pin. The ?40?C to +85?C temperature range LVDS inputs include a 100? internal termination across Output enable (OE) pin the input pair, thus eliminating any need for external Available in 64 EPAD-TQFP termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ APPLICATIONS disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse High-performance PCs when the device is enabled/disabled as can happen with an Workstations asynchronous control. The SY89829U features low pin-to-pin skew (50ps max.) Parallel processor-based systems and low part-to-part skew (200ps max.)?performance Other high-performance computing previously unachievable in a standard product having such Communications a high number of outputs. The SY89829U is available in a Redundant LVPECL or LVDS bus clock switchover single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-011907 1 Issue Date: January 2007 hbwhelp@micrel.com or (408) 955-1690? Precision Edge 2.5V/3.3V HIGH-PERFORMANCE, DUAL 1:10 Micrel, Inc. SY89829U? Precision Edge OR LVPECL CLOCK DRIVER w/ INTERNAL SY89829U TERMINATION AND REDUNDANT SWITCHOVER FEATURES Dual 1:10 fanout buffer/translator ? Precision Edge Accepts LVPECL or LVDS inputs Multiplexed inputs ideal for redundant clock DESCRIPTION switchover Guaranteed AC parameters: The SY89829U is a High Performance dual 1:10 or ? > 2GHz f (toggle) MAX single 1:20 LVPECL Clock Driver. The part is designed for ? < 50ps ch-ch skew use in low voltage (2.5V/3.3V) applications which require a LVDS input includes 100????? internal termination large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed Low supply voltage: 2.5V, 3.3V from either LVDS or LVPECL by the CLK_SEL pin. The ?40?C to +85?C temperature range LVDS inputs include a 100? internal termination across Output enable (OE) pin the input pair, thus eliminating any need for external Available in 64 EPAD-TQFP termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ APPLICATIONS disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse High-performance PCs when the device is enabled/disabled as can happen with an Workstations asynchronous control. The SY89829U features low pin-to-pin skew (50ps max.) Parallel processor-based systems and low part-to-part skew (200ps max.)?performance Other high-performance computing previously unachievable in a standard product having such Communications a high number of outputs. The SY89829U is available in a Redundant LVPECL or LVDS bus clock switchover single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-011907 1 Issue Date: January 2007 hbwhelp@micrel.com or (408) 955-1690VCCO /Q6 Q6 /Q5 Q5 /Q4 Q4 /Q3 Q3 /Q2 Q2 /Q1 Q1 /Q0 Q0 VCCO ? Precision Edge Micrel, Inc. SY89829U PACKAGE/ORDERING INFORMATION (1) Ordering Information 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Package Operating Package Lead 1 48 VCCO SEL2 Part Number Type Range Marking Finish LVDS_CLKB 2 47 Q7 3 46 /Q7 /LVDS_CLKB SY89829UHI H64-1 Industrial SY89829UHI Sn-Pb 4 45 Q8 VCCI 5 44 /Q8 LVDS_CLKA (2) SY89829UHITR H64-1 Industrial SY89829UHI Sn-Pb /LVDS_CLKA 6 43 Q9 7 42 /Q9 CLK_SEL1 64-Pin (3) 8 41 VCCO LVPECL_CLKA SY89829UHY H64-1 Industrial SY89829UHY with Pb-Free EPAD-TQFP 9 40 VCCO /LVPECL_CLKA (Top View) GND 10 39 Q10 Pb-Free bar-line indicator Matte-Sn 11 38 /Q10 OE1 12 37 Q11 LVPECL_CLKB (2, 3) SY89829UHYTR H64-1 Industrial SY89829UHY with Pb-Free /LVPECL_CLKB 13 36 /Q11 14 35 Q12 CLK_SEL2 Pb-Free bar-line indicator Matte-Sn 15 34 /Q12 OE2 16 33 VCCO SEL1 Notes: 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 25 1. Contact factory for die availability. Dice are guaranteed at T = 25?C, DC electricals only. A 2. Tape and Reel. 3. Pb-Free package recommended for new designs. 64-Pin TQFP (H64-1) PIN NAMES Pin Function LVDS_CLKA, Differential LVDS Inputs with Internal 100? Termination. /LVDS_CLKA, LVDS_CLKB, /LVDS_CLKB LVPECL_CLKA, Differential LVPECL Inputs. For DC-coupled input signals, terminate the input signal with 50? to V ?2V. CC /LVPECL_CLKA For AC-coupled to V ?2V. For AC-coupled terminate the input signal with 50? to V ?3V. CC CC LVPECL_CLKB, /LVPECL_CLKB CLK_SEL1, Input CLK Select (LVTTL). CLK_SEL2 SEL1, SEL2 Input Select (LVTTL). OE1, OE2 Output Enable (LVTTL). Q ? Q , /Q ? /Q Differential LVPECL Outputs. Normally terminated with 50? to V ?2V. Unused output pairs can be left 0 19 0 19 CC floating. GND Ground. V Power Supply for Output Drivers. CCI M9999-011907 2 hbwhelp@micrel.com or (408) 955-1690 VCCO /Q19 Q19 /Q18 Q18 /Q16 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 /Q13 Q13 VCCO? Precision Edge 2.5V/3.3V HIGH-PERFORMANCE, DUAL 1:10 Micrel, Inc. SY89829U? Precision Edge OR LVPECL CLOCK DRIVER w/ INTERNAL SY89829U TERMINATION AND REDUNDANT SWITCHOVER FEATURES Dual 1:10 fanout buffer/translator ? Precision Edge Accepts LVPECL or LVDS inputs Multiplexed inputs ideal for redundant clock DESCRIPTION switchover Guaranteed AC parameters: The SY89829U is a High Performance dual 1:10 or ? > 2GHz f (toggle) MAX single 1:20 LVPECL Clock Driver. The part is designed for ? < 50ps ch-ch skew use in low voltage (2.5V/3.3V) applications which require a LVDS input includes 100????? internal termination large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed Low supply voltage: 2.5V, 3.3V from either LVDS or LVPECL by the CLK_SEL pin. The ?40?C to +85?C temperature range LVDS inputs include a 100? internal termination across Output enable (OE) pin the input pair, thus eliminating any need for external Available in 64 EPAD-TQFP termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ APPLICATIONS disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse High-performance PCs when the device is enabled/disabled as can happen with an Workstations asynchronous control. The SY89829U features low pin-to-pin skew (50ps max.) Parallel processor-based systems and low part-to-part skew (200ps max.)?performance Other high-performance computing previously unachievable in a standard product having such Communications a high number of outputs. The SY89829U is available in a Redundant LVPECL or LVDS bus clock switchover single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-011907 1 Issue Date: January 2007 hbwhelp@micrel.com or (408) 955-1690? Precision Edge 2.5V/3.3V HIGH-PERFORMANCE, DUAL 1:10 Micrel, Inc. SY89829U? Precision Edge OR LVPECL CLOCK DRIVER w/ INTERNAL SY89829U TERMINATION AND REDUNDANT SWITCHOVER FEATURES Dual 1:10 fanout buffer/translator ? Precision Edge Accepts LVPECL or LVDS inputs Multiplexed inputs ideal for redundant clock DESCRIPTION switchover Guaranteed AC parameters: The SY89829U is a High Performance dual 1:10 or ? > 2GHz f (toggle) MAX single 1:20 LVPECL Clock Driver. The part is designed for ? < 50ps ch-ch skew use in low voltage (2.5V/3.3V) applications which require a LVDS input includes 100????? internal termination large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed Low supply voltage: 2.5V, 3.3V from either LVDS or LVPECL by the CLK_SEL pin. The ?40?C to +85?C temperature range LVDS inputs include a 100? internal termination across Output enable (OE) pin the input pair, thus eliminating any need for external Available in 64 EPAD-TQFP termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ APPLICATIONS disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse High-performance PCs when the device is enabled/disabled as can happen with an Workstations asynchronous control. The SY89829U features low pin-to-pin skew (50ps max.) Parallel processor-based systems and low part-to-part skew (200ps max.)?performance Other high-performance computing previously unachievable in a standard product having such Communications a high number of outputs. The SY89829U is available in a Redundant LVPECL or LVDS bus clock switchover single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-011907 1 Issue Date: January 2007 hbwhelp@micrel.com or (408) 955-1690VCCO /Q6 Q6 /Q5 Q5 /Q4 Q4 /Q3 Q3 /Q2 Q2 /Q1 Q1 /Q0 Q0 VCCO ? Precision Edge Micrel, Inc. SY89829U PACKAGE/ORDERING INFORMATION (1) Ordering Information 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Package Operating Package Lead 1 48 VCCO SEL2 Part Number Type Range Marking Finish LVDS_CLKB 2 47 Q7 3 46 /Q7 /LVDS_CLKB SY89829UHI H64-1 Industrial SY89829UHI Sn-Pb 4 45 Q8 VCCI 5 44 /Q8 LVDS_CLKA (2) SY89829UHITR H64-1 Industrial SY89829UHI Sn-Pb /LVDS_CLKA 6 43 Q9 7 42 /Q9 CLK_SEL1 64-Pin (3) 8 41 VCCO LVPECL_CLKA SY89829UHY H64-1 Industrial SY89829UHY with Pb-Free EPAD-TQFP 9 40 VCCO /LVPECL_CLKA (Top View) GND 10 39 Q10 Pb-Free bar-line indicator Matte-Sn 11 38 /Q10 OE1 12 37 Q11 LVPECL_CLKB (2, 3) SY89829UHYTR H64-1 Industrial SY89829UHY with Pb-Free /LVPECL_CLKB 13 36 /Q11 14 35 Q12 CLK_SEL2 Pb-Free bar-line indicator Matte-Sn 15 34 /Q12 OE2 16 33 VCCO SEL1 Notes: 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 25 1. Contact factory for die availability. Dice are guaranteed at T = 25?C, DC electricals only. A 2. Tape and Reel. 3. Pb-Free package recommended for new designs. 64-Pin TQFP (H64-1) PIN NAMES Pin Function LVDS_CLKA, Differential LVDS Inputs with Internal 100? Termination. /LVDS_CLKA, LVDS_CLKB, /LVDS_CLKB LVPECL_CLKA, Differential LVPECL Inputs. For DC-coupled input signals, terminate the input signal with 50? to V ?2V. CC /LVPECL_CLKA For AC-coupled to V ?2V. For AC-coupled terminate the input signal with 50? to V ?3V. CC CC LVPECL_CLKB, /LVPECL_CLKB CLK_SEL1, Input CLK Select (LVTTL). CLK_SEL2 SEL1, SEL2 Input Select (LVTTL). OE1, OE2 Output Enable (LVTTL). Q ? Q , /Q ? /Q Differential LVPECL Outputs. Normally terminated with 50? to V ?2V. Unused output pairs can be left 0 19 0 19 CC floating. GND Ground. V Power Supply for Output Drivers. CCI M9999-011907 2 hbwhelp@micrel.com or (408) 955-1690 VCCO /Q19 Q19 /Q18 Q18 /Q16 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 /Q13 Q13 VCCO? Precision Edge Micrel, Inc. SY89829U LOGIC SYMBOL CLK_SEL1 SEL1 OE1 LVDS_CLKA 0 /LVDS_CLKA 10 0 Q ? Q 0 9 LVPECL_CLKA 10 1 /Q ? /Q 0 9 /LVPECL_CLKA 1 LEN LVDS_CLKB Q 0 /LVDS_CLKB D LVPECL_CLKB 1 /LVPECL_CLKB 0 10 Q ? Q 10 19 10 /Q ? /Q 10 19 CLK_SEL2 1 LEN SEL2 Q OE2 D TRUTH TABLE OE CLK_SEL1 CLK_SEL2 SEL1 SEL2 Q ? Q /Q ? /Q Q ? Q /Q ? /Q 0 9 0 9 10 19 10 19 1 0 0 0 0 LVDS_CLKA /LVDS_CLKA LVDS_CLKA /LVDS_CLKA 1 0 0 0 1 LVDS_CLKA /LVDS_CLKA LVDS_CLKB /LVDS_CLKB 1 0 0 1 0 LVDS_CLKB /LVDS_CLKB LVDS_CLKA /LVDS_CLKA 1 0 0 1 1 LVDS_CLKB /LVDS_CLKB LVDS_CLKB /LVDS_CLKB 1 0 1 0 0 LVDS_CLKA /LVDS_CLKA LVDS_CLKA /LVDS_CLKA 1 0 1 0 1 LVDS_CLKA /LVDS_CLKA LVPECL_CLKB /LVPECL_CLKB 1 0 1 1 0 LVPECL_CLKB /LVPECL_CLKB LVDS_CLKA /LVDS_CLKA 1 0 1 1 1 LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB 1 1 0 0 0 LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA 1 1 0 0 1 LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB 1 1 0 1 0 LVDS_CLKB /LVDS_CLKB LVPECL_CLKA /LVPECL_CLKA 1 1 0 1 1 LVDS_CLKB /LVDS_CLKB LVDS_CLKB /LVDS_CLKB 1 1 1 0 0 LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA 1 1 1 0 1 LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB 1 1 1 1 0 LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA 1 1 1 1 1 LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB 0 X X X X LOW HIGH LOW HIGH M9999-011907 3 hbwhelp@micrel.com or (408) 955-1690? Precision Edge 2.5V/3.3V HIGH-PERFORMANCE, DUAL 1:10 Micrel, Inc. SY89829U? Precision Edge OR LVPECL CLOCK DRIVER w/ INTERNAL SY89829U TERMINATION AND REDUNDANT SWITCHOVER FEATURES Dual 1:10 fanout buffer/translator ? Precision Edge Accepts LVPECL or LVDS inputs Multiplexed inputs ideal for redundant clock DESCRIPTION switchover Guaranteed AC parameters: The SY89829U is a High Performance dual 1:10 or ? > 2GHz f (toggle) MAX single 1:20 LVPECL Clock Driver. The part is designed for ? < 50ps ch-ch skew use in low voltage (2.5V/3.3V) applications which require a LVDS input includes 100????? internal termination large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed Low supply voltage: 2.5V, 3.3V from either LVDS or LVPECL by the CLK_SEL pin. The ?40?C to +85?C temperature range LVDS inputs include a 100? internal termination across Output enable (OE) pin the input pair, thus eliminating any need for external Available in 64 EPAD-TQFP termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ APPLICATIONS disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse High-performance PCs when the device is enabled/disabled as can happen with an Workstations asynchronous control. The SY89829U features low pin-to-pin skew (50ps max.) Parallel processor-based systems and low part-to-part skew (200ps max.)?performance Other high-performance computing previously unachievable in a standard product having such Communications a high number of outputs. The SY89829U is available in a Redundant LVPECL or LVDS bus clock switchover single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-011907 1 Issue Date: January 2007 hbwhelp@micrel.com or (408) 955-1690? Precision Edge 2.5V/3.3V HIGH-PERFORMANCE, DUAL 1:10 Micrel, Inc. SY89829U? Precision Edge OR LVPECL CLOCK DRIVER w/ INTERNAL SY89829U TERMINATION AND REDUNDANT SWITCHOVER FEATURES Dual 1:10 fanout buffer/translator ? Precision Edge Accepts LVPECL or LVDS inputs Multiplexed inputs ideal for redundant clock DESCRIPTION switchover Guaranteed AC parameters: The SY89829U is a High Performance dual 1:10 or ? > 2GHz f (toggle) MAX single 1:20 LVPECL Clock Driver. The part is designed for ? < 50ps ch-ch skew use in low voltage (2.5V/3.3V) applications which require a LVDS input includes 100????? internal termination large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed Low supply voltage: 2.5V, 3.3V from either LVDS or LVPECL by the CLK_SEL pin. The ?40?C to +85?C temperature range LVDS inputs include a 100? internal termination across Output enable (OE) pin the input pair, thus eliminating any need for external Available in 64 EPAD-TQFP termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ APPLICATIONS disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse High-performance PCs when the device is enabled/disabled as can happen with an Workstations asynchronous control. The SY89829U features low pin-to-pin skew (50ps max.) Parallel processor-based systems and low part-to-part skew (200ps max.)?performance Other high-performance computing previously unachievable in a standard product having such Communications a high number of outputs. The SY89829U is available in a Redundant LVPECL or LVDS bus clock switchover single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-011907 1 Issue Date: January 2007 hbwhelp@micrel.com or (408) 955-1690VCCO /Q6 Q6 /Q5 Q5 /Q4 Q4 /Q3 Q3 /Q2 Q2 /Q1 Q1 /Q0 Q0 VCCO ? Precision Edge Micrel, Inc. SY89829U PACKAGE/ORDERING INFORMATION (1) Ordering Information 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Package Operating Package Lead 1 48 VCCO SEL2 Part Number Type Range Marking Finish LVDS_CLKB 2 47 Q7 3 46 /Q7 /LVDS_CLKB SY89829UHI H64-1 Industrial SY89829UHI Sn-Pb 4 45 Q8 VCCI 5 44 /Q8 LVDS_CLKA (2) SY89829UHITR H64-1 Industrial SY89829UHI Sn-Pb /LVDS_CLKA 6 43 Q9 7 42 /Q9 CLK_SEL1 64-Pin (3) 8 41 VCCO LVPECL_CLKA SY89829UHY H64-1 Industrial SY89829UHY with Pb-Free EPAD-TQFP 9 40 VCCO /LVPECL_CLKA (Top View) GND 10 39 Q10 Pb-Free bar-line indicator Matte-Sn 11 38 /Q10 OE1 12 37 Q11 LVPECL_CLKB (2, 3) SY89829UHYTR H64-1 Industrial SY89829UHY with Pb-Free /LVPECL_CLKB 13 36 /Q11 14 35 Q12 CLK_SEL2 Pb-Free bar-line indicator Matte-Sn 15 34 /Q12 OE2 16 33 VCCO SEL1 Notes: 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 25 1. Contact factory for die availability. Dice are guaranteed at T = 25?C, DC electricals only. A 2. Tape and Reel. 3. Pb-Free package recommended for new designs. 64-Pin TQFP (H64-1) PIN NAMES Pin Function LVDS_CLKA, Differential LVDS Inputs with Internal 100? Termination. /LVDS_CLKA, LVDS_CLKB, /LVDS_CLKB LVPECL_CLKA, Differential LVPECL Inputs. For DC-coupled input signals, terminate the input signal with 50? to V ?2V. CC /LVPECL_CLKA For AC-coupled to V ?2V. For AC-coupled terminate the input signal with 50? to V ?3V. CC CC LVPECL_CLKB, /LVPECL_CLKB CLK_SEL1, Input CLK Select (LVTTL). CLK_SEL2 SEL1, SEL2 Input Select (LVTTL). OE1, OE2 Output Enable (LVTTL). Q ? Q , /Q ? /Q Differential LVPECL Outputs. Normally terminated with 50? to V ?2V. Unused output pairs can be left 0 19 0 19 CC floating. GND Ground. V Power Supply for Output Drivers. CCI M9999-011907 2 hbwhelp@micrel.com or (408) 955-1690 VCCO /Q19 Q19 /Q18 Q18 /Q16 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 /Q13 Q13 VCCO? Precision Edge 2.5V/3.3V HIGH-PERFORMANCE, DUAL 1:10 Micrel, Inc. SY89829U? Precision Edge OR LVPECL CLOCK DRIVER w/ INTERNAL SY89829U TERMINATION AND REDUNDANT SWITCHOVER FEATURES Dual 1:10 fanout buffer/translator ? Precision Edge Accepts LVPECL or LVDS inputs Multiplexed inputs ideal for redundant clock DESCRIPTION switchover Guaranteed AC parameters: The SY89829U is a High Performance dual 1:10 or ? > 2GHz f (toggle) MAX single 1:20 LVPECL Clock Driver. The part is designed for ? < 50ps ch-ch skew use in low voltage (2.5V/3.3V) applications which require a LVDS input includes 100????? internal termination large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed Low supply voltage: 2.5V, 3.3V from either LVDS or LVPECL by the CLK_SEL pin. The ?40?C to +85?C temperature range LVDS inputs include a 100? internal termination across Output enable (OE) pin the input pair, thus eliminating any need for external Available in 64 EPAD-TQFP termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ APPLICATIONS disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse High-performance PCs when the device is enabled/disabled as can happen with an Workstations asynchronous control. The SY89829U features low pin-to-pin skew (50ps max.) Parallel processor-based systems and low part-to-part skew (200ps max.)?performance Other high-performance computing previously unachievable in a standard product having such Communications a high number of outputs. The SY89829U is available in a Redundant LVPECL or LVDS bus clock switchover single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-011907 1 Issue Date: January 2007 hbwhelp@micrel.com or (408) 955-1690? Precision Edge 2.5V/3.3V HIGH-PERFORMANCE, DUAL 1:10 Micrel, Inc. SY89829U? Precision Edge OR LVPECL CLOCK DRIVER w/ INTERNAL SY89829U TERMINATION AND REDUNDANT SWITCHOVER FEATURES Dual 1:10 fanout buffer/translator ? Precision Edge Accepts LVPECL or LVDS inputs Multiplexed inputs ideal for redundant clock DESCRIPTION switchover Guaranteed AC parameters: The SY89829U is a High Performance dual 1:10 or ? > 2GHz f (toggle) MAX single 1:20 LVPECL Clock Driver. The part is designed for ? < 50ps ch-ch skew use in low voltage (2.5V/3.3V) applications which require a LVDS input includes 100????? internal termination large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed Low supply voltage: 2.5V, 3.3V from either LVDS or LVPECL by the CLK_SEL pin. The ?40?C to +85?C temperature range LVDS inputs include a 100? internal termination across Output enable (OE) pin the input pair, thus eliminating any need for external Available in 64 EPAD-TQFP termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ APPLICATIONS disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse High-performance PCs when the device is enabled/disabled as can happen with an Workstations asynchronous control. The SY89829U features low pin-to-pin skew (50ps max.) Parallel processor-based systems and low part-to-part skew (200ps max.)?performance Other high-performance computing previously unachievable in a standard product having such Communications a high number of outputs. The SY89829U is available in a Redundant LVPECL or LVDS bus clock switchover single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-011907 1 Issue Date: January 2007 hbwhelp@micrel.com or (408) 955-1690VCCO /Q6 Q6 /Q5 Q5 /Q4 Q4 /Q3 Q3 /Q2 Q2 /Q1 Q1 /Q0 Q0 VCCO ? Precision Edge Micrel, Inc. SY89829U PACKAGE/ORDERING INFORMATION (1) Ordering Information 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Package Operating Package Lead 1 48 VCCO SEL2 Part Number Type Range Marking Finish LVDS_CLKB 2 47 Q7 3 46 /Q7 /LVDS_CLKB SY89829UHI H64-1 Industrial SY89829UHI Sn-Pb 4 45 Q8 VCCI 5 44 /Q8 LVDS_CLKA (2) SY89829UHITR H64-1 Industrial SY89829UHI Sn-Pb /LVDS_CLKA 6 43 Q9 7 42 /Q9 CLK_SEL1 64-Pin (3) 8 41 VCCO LVPECL_CLKA SY89829UHY H64-1 Industrial SY89829UHY with Pb-Free EPAD-TQFP 9 40 VCCO /LVPECL_CLKA (Top View) GND 10 39 Q10 Pb-Free bar-line indicator Matte-Sn 11 38 /Q10 OE1 12 37 Q11 LVPECL_CLKB (2, 3) SY89829UHYTR H64-1 Industrial SY89829UHY with Pb-Free /LVPECL_CLKB 13 36 /Q11 14 35 Q12 CLK_SEL2 Pb-Free bar-line indicator Matte-Sn 15 34 /Q12 OE2 16 33 VCCO SEL1 Notes: 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 25 1. Contact factory for die availability. Dice are guaranteed at T = 25?C, DC electricals only. A 2. Tape and Reel. 3. Pb-Free package recommended for new designs. 64-Pin TQFP (H64-1) PIN NAMES Pin Function LVDS_CLKA, Differential LVDS Inputs with Internal 100? Termination. /LVDS_CLKA, LVDS_CLKB, /LVDS_CLKB LVPECL_CLKA, Differential LVPECL Inputs. For DC-coupled input signals, terminate the input signal with 50? to V ?2V. CC /LVPECL_CLKA For AC-coupled to V ?2V. For AC-coupled terminate the input signal with 50? to V ?3V. CC CC LVPECL_CLKB, /LVPECL_CLKB CLK_SEL1, Input CLK Select (LVTTL). CLK_SEL2 SEL1, SEL2 Input Select (LVTTL). OE1, OE2 Output Enable (LVTTL). Q ? Q , /Q ? /Q Differential LVPECL Outputs. Normally terminated with 50? to V ?2V. Unused output pairs can be left 0 19 0 19 CC floating. GND Ground. V Power Supply for Output Drivers. CCI M9999-011907 2 hbwhelp@micrel.com or (408) 955-1690 VCCO /Q19 Q19 /Q18 Q18 /Q16 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 /Q13 Q13 VCCO? Precision Edge Micrel, Inc. SY89829U LOGIC SYMBOL CLK_SEL1 SEL1 OE1 LVDS_CLKA 0 /LVDS_CLKA 10 0 Q ? Q 0 9 LVPECL_CLKA 10 1 /Q ? /Q 0 9 /LVPECL_CLKA 1 LEN LVDS_CLKB Q 0 /LVDS_CLKB D LVPECL_CLKB 1 /LVPECL_CLKB 0 10 Q ? Q 10 19 10 /Q ? /Q 10 19 CLK_SEL2 1 LEN SEL2 Q OE2 D TRUTH TABLE OE CLK_SEL1 CLK_SEL2 SEL1 SEL2 Q ? Q /Q ? /Q Q ? Q /Q ? /Q 0 9 0 9 10 19 10 19 1 0 0 0 0 LVDS_CLKA /LVDS_CLKA LVDS_CLKA /LVDS_CLKA 1 0 0 0 1 LVDS_CLKA /LVDS_CLKA LVDS_CLKB /LVDS_CLKB 1 0 0 1 0 LVDS_CLKB /LVDS_CLKB LVDS_CLKA /LVDS_CLKA 1 0 0 1 1 LVDS_CLKB /LVDS_CLKB LVDS_CLKB /LVDS_CLKB 1 0 1 0 0 LVDS_CLKA /LVDS_CLKA LVDS_CLKA /LVDS_CLKA 1 0 1 0 1 LVDS_CLKA /LVDS_CLKA LVPECL_CLKB /LVPECL_CLKB 1 0 1 1 0 LVPECL_CLKB /LVPECL_CLKB LVDS_CLKA /LVDS_CLKA 1 0 1 1 1 LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB 1 1 0 0 0 LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA 1 1 0 0 1 LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB 1 1 0 1 0 LVDS_CLKB /LVDS_CLKB LVPECL_CLKA /LVPECL_CLKA 1 1 0 1 1 LVDS_CLKB /LVDS_CLKB LVDS_CLKB /LVDS_CLKB 1 1 1 0 0 LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA 1 1 1 0 1 LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB 1 1 1 1 0 LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA 1 1 1 1 1 LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB 0 X X X X LOW HIGH LOW HIGH M9999-011907 3 hbwhelp@micrel.com or (408) 955-1690

Tariff Concession Code
Tariff Desc

Free
8542.31.00 61 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products8542.31.00

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