2x INTERPOLATING FILTERS MODULATOR 1x/2x/4x INTERPOLATING FILTERS DATA SYNCH AND DEMUX MAX5893 19-3546 Rev 2 10/08 12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs General Description Features The MAX5893 programmable interpolating, modulating, 72dB ACLR at f = 61.44MHz (Single-Carrier OUT 500Msps, dual digital-to-analog converter (DAC) offers WCDMA) superior dynamic performance and is optimized for high- Meets 3G UMTS, cdma2000 , GSM Spectral Masks performance wideband, single-carrier transmit applica- (f = 122MHz) OUT tions. The device integrates a selectable 2x/4x/8x Noise Spectral Density = -151dBFS/Hz at interpolating filter, a digital quadrature modulator, and f = 16MHz OUT dual 12-bit high-speed DACs on a single integrated cir- cuit. At 30MHz output frequency and 500Msps update 90dBc SFDR at Low-IF Frequency (10MHz) rate, the in-band SFDR is 84dBc while consuming 1.1W. 86dBc SFDR at High-IF Frequency (50MHz) The device also delivers 72dB ACLR for single-carrier Low Power: 511mW (f = 100MHz) CLK WCDMA at a 61.44MHz output frequency. User Programmable The selectable interpolating filters allow lower input data Selectable 2x, 4x, or 8x Interpolating Filters rates while taking advantage of the high DAC update < 0.01dB Passband Ripple rates. These linear-phase interpolation filters ease > 99dB Stopband Rejection reconstruction filter requirements and enhance the Selectable Real or Complex Modulator Operation passband dynamic performance. Individual offset and Selectable Modulator LO Frequency: OFF, f /2, IM gain programmability allow the user to calibrate out local or f /4 IM oscillator (LO) feedthrough and sideband suppression Selectable Output Filter: Lowpass or Highpass errors generated by analog quadrature modulators. Channel Gain and Offset Adjustment The MAX5893 features a f /4 digital image-reject mod- IM EV Kit Available (Order the MAX5893EVKIT) ulator. This modulator generates a quadrature-modulat- ed IF signal that can be presented to an analog I/Q Ordering Information modulator to complete the upconversion process. A second digital modulation mode allows the signal to be PART TEMP RANGE PIN-PACKAGE frequency-translated with image pairs at f /2 or f /4. IM IM MAX5893EGK-D -40C to +85C 68 QFN-EP* The MAX5893 features a standard 1.8V CMOS, 3.3V tol- MAX5893EGK+D -40C to +85C 68 QFN-EP* erant data input bus for easy interface. A 3.3V SPI port D = Dry pack. is provided for mode configuration. The programmable *EP = Exposed pad. modes include the selection of 2x/4x/8x interpolating fil- +Denotes a lead-free/RoHS-compliant package. ters, f /2, f /4 or no digital quadrature modulation with IM IM image rejection, channel gain and offset adjustment, and Selector Guide offset binary or twos complement data interface. Pin-compatible 14- and 16-bit devices are also available. RESOLUTION DAC UPDATE INPUT PART Refer to the MAX5894 data sheet for the 14-bit version (BITS) RATE (Msps) LOGIC and the MAX5895 data sheet for the 16-bit version. MAX5893 12 500 CMOS Applications MAX5894 14 500 CMOS Base Stations: 3G UMTS, CDMA, and GSM MAX5895 16 500 CMOS Broadband Wireless Transmitters MAX5898 16 500 LVDS Broadband Cable Infrastructure Simplified Diagram Instrumentation and Automatic Test Equipment (ATE) Analog Quadrature Modulation Architectures OUTI DATA DAC PORT A Pin Configuration appears at end of data sheet. DATACLK DATA SPI is a trademark of Motorola, Inc. DAC PORT B OUTQ cdma2000 is a registered trademark of Telecommunications Industry Association. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. EVALUATION KIT AVAILABLE12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS DV , AV to GND, DACREF ..................-0.3V to +2.16V SDO, DATACLK, DATACLK/BIO Continuous Current ..........8mA DD1.8 DD1.8 AV , AV , DV to GND, DACREF........-0.3V to +3.9V Continuous Power Dissipation (T = +70C) DD3.3 CLK DD3.3 A DATACLK, A0A11, B0B9, 68-Pin QFN (derate 41.7mW/C above +70C) SELIQ/B11, DATACLK/B10, CS, RESET, SCLK, (Note 1) ...................................................................3333.3mW SDI and SDO to GND, DACREF......-0.3V to (DV + 0.3V) Junction Temperature......................................................+150C DD3.3 CLKP, CLKN to GND, DACREF..............-0.3V to (AV + 0.3V) Operating Temperature Range ...........................-40C to +85C CLK REFIO, FSADJ to GND, DACREF ........-0.3V to (AV + 0.3V) Storage Temperature Range .............................-65C to +150C DD3.3 OUTIP, OUTIN, OUTQP, Lead Temperature (soldering, 10s) .................................+300C OUTQN to GND, DACREF..................-1V to (AV + 0.3V) Thermal Resistance (Note 1)....................................0.8C/W DD3.3 JC Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed pad area. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (DV = AV = 1.8V, AV = AV = DV = 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port DD1.8 DD1.8 CLK DD3.3 DD3.3 mode, 50 double-terminated outputs, external reference at 1.25V, T = -40C to +85C, unless otherwise noted. Typical values are A at T = +25C, unless otherwise noted.) (Note 2) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 12 Bits Differential Nonlinearity DNL 0.5 LSB Integral Nonlinearity INL 1 LSB Offset Error OS -0.025 0.003 +0.025 %FS Offset Drift 0.03 ppm/C Full-Scale Gain Error GE -4 0.6 +4 %FS FS Gain-Error Drift 110 ppm/C Full-Scale Output Current I 220mA OUTFS Output Compliance -0.5 +1.1 V Output Resistance R 1M OUT Output Capacitance C 5pF OUT DYNAMIC PERFORMANCE Maximum Clock Frequency f 500 MHz CLK Minimum Clock Frequency f 1 MHz CLK Maximum DAC Update Rate f f = f or f = f /2 500 Msps DAC DAC CLK DAC CLK Minimum DAC Update Rate f f = f or f = f /2 1 Msps DAC DAC CLK DAC CLK Maximum Input Data Rate f 125 MWps DATA No interpolation -151 f = 125MHz, DATACLK f = 16MHz, f 2x interpolation -147 OUT OFFSET = 10MHz, -12dBFS 4x interpolation -148 dBFS/ Noise Spectral Density Hz f = 125MHz, DATACLK f = 16MHz, f 4x interpolation -145 OUT OFFSET = 10MHz, 0dBFS 2 MAX5893