MAX5864 19-2915 Rev 1 10/03 Ultra-Low-Power, High-Dynamic- Performance, 22Msps Analog Front End General Description Features The MAX5864 ultra-low-power, highly integrated analog Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs front end is ideal for portable communication equipment Ultra-Low Power such as handsets, PDAs, WLAN, and 3G wireless termi- 42mW at f = 22MHz (Transceiver Mode) nals. The MAX5864 integrates dual 8-bit receive ADCs CLK and dual 10-bit transmit DACs while providing the high- 34mW at f = 15.36MHz (Transceiver Mode) CLK est dynamic performance at ultra-low power. The ADCs Low-Current Idle and Shutdown Modes analog I-Q input amplifiers are fully differential and Excellent Dynamic Performance accept 1V full-scale signals. Typical I-Q channel P-P 48.5dB SINAD at f = 5.5MHz (ADC) IN phase matching is 0.1 and amplitude matching is 71.7dB SFDR at f = 2.2MHz (DAC) OUT 0.03dB. The ADCs feature 48.5dB SINAD and 69dBc spurious-free dynamic range (SFDR) at f = 5.5MHz and IN Excellent Gain/Phase Match f = 22Msps. The DACs analog I-Q outputs are fully CLK 0.1 Phase, 0.03dB Gain at f = 5.5MHz (ADC) IN differential with 400mV full-scale output, and 1.4V com- Internal/External Reference Option mon-mode level. Typical I-Q channel phase match is 0.15 and amplitude match is 0.05dB. The DACs also +1.8V to +3.3V Digital Output Level (TTL/CMOS feature dual 10-bit resolution with 71.7dBc SFDR, and Compatible) 57dB SNR at f = 2.2MHz and f = 22MHz. OUT CLK Multiplexed Parallel Digital Input/Output for The ADCs and DACs operate simultaneously or indepen- ADCs/DACs dently for frequency-division duplex (FDD) and time-divi- sion duplex (TDD) modes. A 3-wire serial interface Miniature 48-Pin Thin QFN Package (7mm 7mm) controls power-down and transceiver modes of opera- Evaluation Kit Available (Order MAX5865EVKIT) tion. The typical operating power is 42mW at f = CLK 22Msps with the ADCs and DACs operating simultane- ously in transceiver mode. The MAX5864 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5864 operates on a +2.7V to +3.3V ana- Functional Diagram log power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 5.6mA in idle mode and 1A in shutdown mode. The MAX5864 is specified for the extended (-40C to +85C) IA+ ADC temperature range and is available in a 48-pin thin QFN IA- ADC package. OUTPUT DA0DA7 MUX QA+ ADC Applications QA- Narrowband/Wideband CDMA Handsets CLK and PDAs ID+ DAC Fixed/Mobile Broadband Wireless Modems ID- DAC INPUT DD0DD9 3G Wireless Terminals MUX QD+ DAC Ordering Information QD- REFP PART TEMP RANGE PIN-PACKAGE COM REFN SERIAL 48 Thin QFN-EP* DIN MAX5864ETM -40C to +85C INTERFACE (7mm x 7mm) SCLK REF AND AND SYSTEM REFIN CS BIAS CONTROL MAX5864E/D -40C to +85C Dice** *EP = Exposed paddle. MAX5864 **Contact factory for dice specifications. Pin Configuration appears at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. EVALUATION KIT AVAILABLEUltra-Low-Power, High Dynamic- Performance, 22Msps Analog Front End ABSOLUTE MAXIMUM RATINGS V to GND, OV to OGND................................-0.3V to +3.3V Continuous Power Dissipation (T = +70C) DD DD A GND to OGND.......................................................-0.3V to +0.3V 48-Pin Thin QFN (derate 26.3mW/C above +70C) ..........2.1W IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, Thermal Resistance .................................................+38C/W JA REFIN, COM to GND..............................-0.3V to (V + 0.3V) Operating Temperature Range ...........................-40C to +85C DD DD0DD9, SCLK, DIN, CS, CLK, Junction Temperature......................................................+150C DA0DA7 to OGND .............................-0.3V to (OV + 0.3V) Storage Temperature Range .............................-60C to +150C DD Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V = 3V, OV = 1.8V, internal reference (1.024V), C 10pF on all digital outputs, f = 22MHz, ADC input amplitude = -0.5dBFS, DD DD L CLK DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C = C = C = 0.33F, Xcvr mode, unless REFP REFN COM otherwise noted. Typical values are at T = +25C, unless otherwise noted.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage V 2.7 3.0 3.3 V DD Output Supply Voltage OV 1.8 V V DD DD ADC oper at ing m ode, f = 5.5MH z, f = IN C LK 14 16.5 22M H z, DAC op er ating m ode, f = 2.2MH z OUT ADC oper at ing m ode, f = 5.5MH z, f = IN C LK 15.36MH z, DAC op er ati ng m ode, f = 11.4 OUT 2.2MH z ADC operating mode (Rx), f = 5.5MH z, IN f = 15.36MH z, DAC off, DAC digital 8.25 CLK mA inputs at zero or DV DD V Supply Current DD DAC operating mode (Tx), f = 2.2MHz, OUT 8 f = 15.36MH z, ADC off CLK Standby mode, DAC digital inputs and CLK 2.0 at zero or OV DD Idle mode, DAC digital inputs at zero or 6.7 OV , f = 22MHz DD CLK Shutdown mode, digital inputs and CLK at 1A zero or OV , CS = OV DD DD ADC operating mode, f = 5.5MHz, f = IN CLK 2.3 mA 22MHz, DAC operating mode, f = 2.2MHz OUT Idle mode, DAC digital inputs at zero or OV Supply Current 20.6 DD OV f = 22MHz DD, CLK A Shutdown mode, DAC digital inputs and 1 CLK at zero or OV , CS = OV DD DD 2 MAX5864