M24LR64E-RMN6T/2

M24LR64E-R Dynamic NFC/RFID tag IC with 64-Kbit EEPROM, energy harvesting, IC bus and ISO 15693 RF interface Datasheet - production data in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with Fast commands Internal tuning capacitance: 27.5 pF SO8 (MN) UFDFPN8 (MC) 64-bit unique identifier (UID) TSSOP8 (DW) 2 x 3 mm Read Block & Write (32-bit blocks) Digital output pin User configurable pin: RF write in progress or RF busy mode Energy harvesting Wafer (SB12I) Wafer (RUW20) Analog pin for energy harvesting Four sink current configurable ranges Features Belonging to ST25 family, which includes all Temperature range NFC/RF ID tag and reader products from ST From 40 to 85 C 2 I C interface Memory 2 Two-wires I C serial interface supports 64-Kbit EEPROM organized into: 400 kHz protocol 2 8192 bytes in I C mode Single supply voltage: 2048 blocks of 32 bits in RF mode 1.8 V to 5.5 V Write time Byte and Page Write (up to 4 bytes) 2 I C: 5 ms (max.) Random and Sequential read modes RF: 5.75 ms including the internal Verify Self-timed programming cycle time Automatic address incrementing Write cycling endurance: 1 million write cycles at 25 C Enhanced ESD/latch-up protection 150 k write cycles at 85 C IC timeout More than 40-year data retention Contactless interface Multiple password protection in RF mode 2 ISO 15693 and ISO 18000-3 mode 1 compatible Single password protection in I C mode 13.56 MHz 7 kHz carrier frequency Package To tag: 10% or 100% ASK modulation using 1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse position coding SO8 (ECOPACK2 ) From tag: load modulation using Manchester TSSOP8 (ECOPACK2 ) coding with 423 kHz and 484 kHz subcarriers UFDFPN8 (ECOPACK2 ) July 2017 DocID022712 Rev 12 1/144 This is information on a product in full production. www.st.com 1Contents M24LR64E-R Contents 1 Description 13 2 Signal descriptions . 15 2.1 Serial clock (SCL) . 15 2.2 Serial data (SDA) . 15 2.3 RF Write in progress / RF Busy (RF WIP/BUSY) . 15 2.4 Energy harvesting analog output (Vout) 15 2.5 Antenna coil (AC0, AC1) . 15 2.5.1 Device reset in RF mode 15 2.6 V ground 16 SS 2.7 Supply voltage (V ) 16 CC 2.7.1 Operating supply voltage V CC . 16 2.7.2 Power-up conditions . 16 2.7.3 Device reset in IC mode 16 2.7.4 Power-down conditions . 16 3 User memory organization . 19 4 System memory area . 24 4.1 M24LR64E-R block security in RF mode . 24 4.1.1 Example of the M24LR64E-R security protection in RF mode . 26 4.2 M24LR64E-R block security in IC mode (I2C Write Lock bit area) 27 4.3 Configuration byte and Control register 27 4.3.1 RF WIP/BUSY pin configuration 27 4.3.2 Energy harvesting configuration 28 4.3.3 FIELD ON indicator bit . 30 4.3.4 Configuration byte access in IC and RF modes 30 4.3.5 Control register access in IC or RF mode 30 4.4 ISO 15693 system parameters . 30 2 5I C device operation 32 5.1 Start condition 32 5.2 Stop condition 32 2/144 DocID022712 Rev 12