MachXO3 Family Data Sheet Advance DS1047 Version 1.3, March 2015MachXO3 Family Data Sheet Introduction March 2015 Advance Data Sheet DS1047 Features Solutions Flexible On-Chip Clocking Smallest footprint, lowest power, high data Eight primary clocks throughput bridging solutions for mobile applica- Up to two edge clocks for high-speed I/O inter- tions faces (top and bottom sides only) Optimized footprint, logic density, IO count, IO Up to two analog PLLs per device with frac- performance devices for IO management and tional-n frequency synthesis logic applications Wide input frequency range High IO/logic, lowest cost/IO, high IO devices for (7 MHz to 400 MHz) IO expansion applications Non-volatile, Multi-time Programmable Flexible Architecture Instant-on Logic Density ranging from 640 to 6.9K LUT4 Powers up in microseconds High IO to LUT ratio with up to 335 IO pins Optional dual boot with external SPI memory Single-chip, secure solution Advanced Packaging 2 Programmable through JTAG, SPI or I C 0.4 mm pitch: 1K to 4K densities in very small MachXO3L includes multi-time programmable footprint WLCSP (2.5 mm x 2.5 mm to NVCM 3.8 mm x 3.8 mm) with 28 to 63 IOs MachXO3LF infinitely reconfigurable Flash 0.5 mm pitch: 640 to 6.9K LUT densities in Supports background programming of non- 6 mm x 6 mm to 10 mm x 10 mm BGA packages volatile memory with up to 281 IOs 0.8mm pitch: 1K to 6.9K densities with up to 335 TransFR Reconfiguration IOs in BGA packages In-field logic update while IO holds the system Pre-Engineered Source Synchronous I/O state DDR registers in I/O cells Enhanced System Level Support Dedicated gearing logic 2 On-chip hardened functions: SPI, I C, timer/ 7:1 Gearing for Display I/Os counter Generic DDR, DDRx2, DDRx4 On-chip oscillator with 5.5% accuracy High Performance, Flexible I/O Buffer Unique TraceID for system tracking TM Single power supply with extended operating Programmable sysIO buffer supports wide range range of interfaces: IEEE Standard 1149.1 boundary scan LVCMOS 3.3/2.5/1.8/1.5/1.2 IEEE 1532 compliant in-system programming LVTTL LVDS, Bus-LVDS, MLVDS, LVPECL Applications MIPI D-PHY Emulated Consumer Electronics Schmitt trigger inputs, up to 0.5 V Compute and Storage hysteresis Wireless Communications Ideal for IO bridging applications Industrial Control Systems I/Os support hot socketing Automotive System On-chip differential termination Low Cost Migration Path Programmable pull-up or pull-down mode Migration from the Flash based MachXO3LF to the NVCM based MachXO3L Pin compatible and equivalent timing 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1047 Introduction 0.6