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EVAL-ADCMP562BRQZ

EVAL-ADCMP562BRQZ electronic component of Analog Devices

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Amplifier IC Development Tools EVALUATION BOARD-HIGH SPEED COMPARATO

Manufacturer: Analog Devices
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1: USD 70.8422 ea
Line Total: USD 70.8422

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EVAL-ADCMP562BRQZ
Analog Devices

1 : USD 86.1405

     
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Dual High Speed PECL Comparators Data Sheet ADCMP561/ADCMP562 FEATURES FUNCTIONAL BLOCK DIAGRAM HYS* Differential PECL-compatible outputs 700 ps propagation delay input to output NONINVERTING Q OUTPUT INPUT 75 ps propagation delay dispersion ADCMP561/ Input common-mode range: 2.0 V to +3.0 V ADCMP562 Robust input protection INVERTING Q OUTPUT INPUT Differential latch control Internal latch pull-up resistors LATCH ENABLE LATCH ENABLE Power supply rejection greater than 85 dB INPUT INPUT 700 ps minimum pulse width *ADCMP562 ONLY 1.5 GHz equivalent input rise time bandwidth Figure 1. Typical output rise/fall time of 500 ps ESD protection > 4 kV HBM, >200 V MM 1 16 QB QA Programmable hysteresis 2 15 QB QA 3 14 GND V DD APPLICATIONS ADCMP561 LEA 4 13 LEB Automatic test equipment TOP VIEW LEA 5 12 LEB (Not to Scale) High speed instrumentation 6 11 V V CC EE Scope and logic analyzer front ends 7 10 INB INA Window comparators 8 9 +INB +INA High speed line receivers Threshold detection Figure 2. ADCMP561 16-Lead QSOP Pin Configuration Peak detection High speed triggers V 1 20 V DD DD Patient diagnostics QA 2 19 QB Disk drive read channel detection QA 3 18 QB ADCMP562 Hand-held test instruments V 4 17 GND DD TOP VIEW LEA LEB Zero-crossing detectors 5 16 (Not to Scale) LEA LEB Line receivers and signal restoration 6 15 V 7 14 V Clock drivers EE CC INA 8 13 INB +INA 9 12 +INB HYSA HYSB 10 11 Figure 3. ADCMP562 20-Lead QSOP Pin Configuration GENERAL DESCRIPTION The ADCMP561/ADCMP562 are high speed comparators to +3.0 V. Outputs are complementary digital signals that are fully fabricated on Analog Devices, Inc., proprietary XFCB process. The compatible with PECL 10 K and 10 KH logic families. The outputs devices feature a 700 ps propagation delay with less than 75 ps provide sufficient drive current to directly drive transmission lines overdrive dispersion. Dispersion, a measure of the difference in terminated in 50 to V DD 2 V. A latch input, which is included, propagation delay under differing overdrive conditions, is a permits tracking, track-and-hold, or sample-and-hold modes of particularly important characteristic of comparators. A separate operation. The latch input pins contain internal pull-ups that set programmable hysteresis pin is available on the ADCMP562. the latch in tracking mode when left open. A differential input stage permits consistent propagation delay with The ADCMP561/ADCMP562 are specified over the industrial a wide variety of signals in the common-mode range from 2.0 V temperature range (40C to +85C). Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 04687-0-002 04687-0-003 04687-0-001ADCMP561/ADCMP562 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timing Information ....................................................................... 10 Applications ....................................................................................... 1 Applications Information ............................................................... 11 Functional Block Diagram .............................................................. 1 Clock Timing Recovery .............................................................. 11 General Description ......................................................................... 1 Optimizing High Speed Performance ...................................... 11 Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ............................ 11 Specifications ..................................................................................... 3 Comparator Hysteresis .............................................................. 12 Absolute Maximum Ratings ............................................................ 5 Minimum Input Slew Rate Requirement ................................ 12 Thermal Considerations .............................................................. 5 Typical Application Circuits .......................................................... 13 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 14 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 14 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 2/2017Data Sheet Changed from Rev. A to Rev. B Updated Format .................................................................. Universal Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 7/2004Data Sheet Changed from Rev. 0 to Rev. A Changes to Specification Table ....................................................... 4 Changes to Figure 14 ........................................................................ 9 Changes to Figure 21 ...................................................................... 12 Changes to Figure 23 ...................................................................... 13 4/2004Revision 0: Initial Version Rev. B Page 2 of 14

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