6.2 GHz Fractional-N Frequency Synthesizer Data Sheet ADF4156 FEATURES GENERAL DESCRIPTION RF bandwidth to 6.2 GHz The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer 2.7 V to 3.3 V power supply that implements local oscillators in the upconversion and down- Separate V pin allows extended tuning voltage P conversion sections of wireless receivers and transmitters. It Programmable fractional modulus consists of a low noise digital phase frequency detector (PFD), a Programmable charge-pump currents precision charge pump, and a programmable reference divider. 3-wire serial interface There is a - based fractional interpolator to allow programmable Digital lock detect fractional-N division. The INT, FRAC, and MOD registers define Power-down mode an overall N divider (N = (INT + (FRAC/MOD))). The RF output Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113, phase is programmable for applications that require a particular ADF4106, ADF4153, and ADF4154 frequency synthesizers phase relationship between the output and the reference. The Programmable RF output phase ADF4156 also features cycle slip reduction circuitry, leading Loop filter design possible with ADIsimPLL to faster lock times without the need for modifications to the Cycle slip reduction for faster lock times loop filter. APPLICATIONS Control of all on-chip registers is via a simple 3-wire interface. CATV equipment The device operates with a power supply ranging from 2.7 V to Base stations for mobile radio (WiMAX, GSM, PCS, DCS, 3.3 V and can be powered down when not in use. SuperCell 3G, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, PMR Communications test equipment FUNCTIONAL BLOCK DIAGRAM AV DV V R DD DD P SET ADF4156 REFERENCE 5-BIT 2 REF R-COUNTER IN DOUBLER /2 + DIVIDER PHASE CP FREQUENCY CHARGE DETECTOR PUMP V DD HIGH Z DGND CSR LOCK CURRENT DETECT SETTING OUTPUT MUXOUT SD OUT MUX V DD RFCP4 RFCP3 RFCP2 RFCP1 R DIV RF A IN N-COUNTER N DIV RF B IN THIRD-ORDER FRACTIONAL CE INTERPOLATOR CLOCK FRACTION MODULUS INTEGER 32-BIT REG REG REG DATA DATA REGISTER LE AGND DGND CPGND Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 05863-001ADF4156 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Maps .................................................................................. 10 Applications ....................................................................................... 1 FRAC/INT Register, R0 ............................................................. 11 General Description ......................................................................... 1 Phase Register, R1 ...................................................................... 12 Functional Block Diagram .............................................................. 1 MOD/R Register, R2 .................................................................. 13 Revision History ............................................................................... 2 Function Register, R3 ................................................................. 15 Specifications ..................................................................................... 3 CLK DIV Register, R4 ................................................................ 16 Timing Specifications .................................................................. 4 Reserved Bits ............................................................................... 16 Absolute Maximum Ratings ............................................................ 5 Initialization Sequence .............................................................. 16 Thermal Impedance ..................................................................... 5 RF Synthesizer: A Worked Example ........................................ 17 ESD Caution .................................................................................. 5 Modulus ....................................................................................... 17 Pin Configurations and Function Descriptions ........................... 6 Reference Doubler and Reference Divider ............................. 17 Typical Performance Characteristics ............................................. 7 12-Bit Programmable Modulus ................................................ 17 Circuit Description ........................................................................... 8 Fast Lock Times with the ADF4156 ........................................ 17 Reference Input Section ............................................................... 8 Spur Mechanisms ....................................................................... 19 RF Input Stage ............................................................................... 8 Spur Consistency and Fractional Spur Optimization ........... 19 RF INT Divider ............................................................................. 8 Phase Resync ............................................................................... 20 INT, FRAC, MOD, and R Relationship ..................................... 8 Low Frequency Applications .................................................... 20 RF R-Counter ................................................................................ 8 Filter DesignADIsimPLL ....................................................... 20 Phase Frequency Detector (PFD) and Charge Pump .............. 9 Interfacing ................................................................................... 21 MUXOUT and Lock Detect ........................................................ 9 PCB Design Guidelines for Chip Scale Package .................... 21 Input Shift Registers ..................................................................... 9 Outline Dimensions ....................................................................... 22 Program Modes ............................................................................ 9 Ordering Guide .......................................................................... 22 REVISION HISTORY 10/13Rev. D. to Rev. E Change to Program Modes Section ................................................ 9 Changes to Table 3 ............................................................................ 5 Changes to Figure 16 ...................................................................... 10 Updated Outline Dimensions ....................................................... 22 Changes to Figure 17 ...................................................................... 11 Changes to Ordering Guide .......................................................... 22 Changes to CSR Enable Section ................................................... 13 3/12Rev. C to Rev. D Changes to Figure 19 ...................................................................... 14 Changes to Table 1 ............................................................................ 3 Changes to Function Register, R3 Section and Figure 20 ......... 15 Changes to Ordering Guide .......................................................... 22 Changes to 12-Bit Clock Divider Value Section, to 9/11Rev. B to Rev. C Clock Divider Mode Section, and to Figure 21 .......................... 16 Changes to Noise Characteristics Parameter ................................ 3 Changes to Reference Doubler and Reference Divider Section 4/11Rev. A to Rev. B and to Fast Lock Times with the ADF4156 Section .................. 17 Changes to Product Title, Features Section and General Added Figure 22 and Figure 23 Renumbered Sequentially ..... 19 Description Section .......................................................................... 1 Change to Phase Resync Section .................................................. 20 Changes to RF Input Frequency RFIN Parameter, Table 1 ........... 3 Changes to Interfacing Section and to PCB Design Guidelines Changes to Figure 4 and Table 5 ..................................................... 6 for Chip Scale Package Section ..................................................... 21 5/09Rev. 0 to Rev. A Changes to Outline Dimensions .................................................. 23 Added Low Power Sleep Mode Parameter and Changes to Changes to Ordering Guide .......................................................... 23 Endnote 4, Table 1 ............................................................................ 3 5/06Revision 0: Initial Version Change to Figure 9 Caption ............................................................ 7 Rev. E Page 2 of 24