Product Information

AD9540BCPZ

AD9540BCPZ electronic component of Analog Devices

Datasheet
Clock Generators & Support Products Low Jitter DDS-based & Synthesizer

Manufacturer: Analog Devices
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

26: USD 27.5175 ea
Line Total: USD 715.455

0 - Global Stock
MOQ: 26  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Thu. 04 Apr to Wed. 10 Apr

MOQ : 25
Multiples : 25

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AD9540BCPZ
Analog Devices

25 : USD 72.4022

0 - Global Stock


Ships to you between Wed. 10 Apr to Fri. 12 Apr

MOQ : 1
Multiples : 1

Stock Image

AD9540BCPZ
Analog Devices

1 : USD 51.3072
10 : USD 45.4932
25 : USD 43.4579
100 : USD 38.8541
250 : USD 37.0609
500 : USD 36.1766

     
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655 MHz Low Jitter Clock Generator Data Sheet AD9540 FEATURES APPLICATIONS Excellent intrinsic jitter performance Clocking high performance data converters 200 MHz phase frequency detector inputs Base station clocking applications 655 MHz programmable input dividers for the phase Network (SONET/SDH) clocking frequency detector (M, N) M, N = 1 to 16 (bypassable) Gigabit Ethernet (GbE) clocking Programmable RF divider (R) R = 1, 2, 4, 8 (bypassable) Instrumentation clocking circuits 8 programmable phase/frequency profiles Agile LO frequency synthesis 400 MSPS internal DDS clock speed Automotive radar 48-bit frequency tuning word resolution FM chirp source for radar and scanning systems 14-bit programmable phase offset Test and measurement equipment 1.8 V supply for device operation Acousto-optic device drivers 3.3 V supply for I/O, CML driver, and charge pump output Software controlled power-down 48-lead LFCSP package Programmable charge pump current (up to 4 mA) Dual-mode PLL lock detect 655 MHz CML-mode PECL-compliant output driver FUNCTIONAL BLOCK DIAGRAM AVDD AGND DVDD DGND CP VDD CP RSET CP REF, AMP REFIN M DIVIDER PHASE REFIN CHARGE CP OUT FREQUENCY PUMP DETECTOR N DIVIDER CLK2 SYNC, PLL SYNC IN/STATUS LOCK CLK2 CLK1 DRV RSET CML CLK1 OUT0 DIVIDER 1, 2, 4, 8 OUT0 SCLK SERIAL SDI/O CONTROL AD9540 SDO PORT CS CLK TIMING AND DIVCLK CONTROL LOGIC S2 48 PHASE/ IOUT 10 S1 FREQUENCY DDS DAC 14 PROFILES IOUT S0 DAC RSET Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20042020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 04947-001AD9540 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PLL Circuitry .............................................................................. 19 Applications ...................................................................................... 1 CML Driver ................................................................................. 19 Functional Block Diagram .............................................................. 1 DDS and DAC ............................................................................ 20 Revision History ............................................................................... 2 Modes of Operation ....................................................................... 21 Product Overview ............................................................................. 3 Selectable Clock Frequencies and Selectable Edge Delay ..... 21 Specifications .................................................................................... 4 Synchronization Modes for Multiple Devices ............................. 21 Loop Measurement Conditions ................................................. 8 Serial Port Operation ..................................................................... 22 Absolute Maximum Ratings ........................................................... 9 Instruction Byte .......................................................................... 23 ESD Caution.................................................................................. 9 Serial Interface Port Pin Description ...................................... 23 Pin Configuration and Function Descriptions .......................... 10 MSB/LSB Transfers .................................................................... 23 Typical Performance Characteristics ........................................... 12 Register Map and Description ...................................................... 24 Typical Application Circuits ......................................................... 17 Control Register Bit Descriptions ............................................ 27 Application Circuit Descriptions ............................................. 18 Outline Dimensions ....................................................................... 32 Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 32 REVISION HISTORY 9/2020Rev. C to Rev. D 9/2016Rev. A to Rev. B Changed CP-48-1 to CP-48-4 ...................................... Throughout Change to Features ............................................................................ 1 Changes to Figure 3 ........................................................................ 10 Updated Outline Dimensions ...................................................... 32 Updated Outline Dimensions ....................................................... 33 Changes to Ordering Guide .......................................................... 32 Changes to Ordering Guide .......................................................... 33 2/2006Rev. 0 to Rev. A 4/2018Rev. B to Rev. C Changes to Features Section ............................................................ 1 Changes to Figure 3 ........................................................................ 10 Changes to Applications Section .................................................... 1 Updated Outline Dimensions ....................................................... 32 Changes to Functional Block Diagram .......................................... 1 Changes to Ordering Guide .......................................................... 32 Changes to Table 1 ............................................................................ 4 Changes to Typical Application Circuits Section ...................... 17 Updates to Ordering Guide .......................................................... 32 7/2004Revision 0: Initial Version Rev. D Page 2 of 32

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
AD4
ANALOG DEVICES
Analog Devices Hittite
ANALOG DEVICES (LINEAR TECHNOLOGY)
ANALOG DEVICES (MAXIM INTEGRATED)
ANALOG DEVICES (TRINAMIC)
Analog Devices / Hittite
Analog Devices / Linear Technology
Analog Devices Inc
Analog Devices Inc.
Analog Devices, Inc.
DA4
Dallas
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Dallas Semiconductor (VA)
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Linear Technology (part of ADI)
LT
LT4
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Maxim Integrated Products
MAXIM-DALLAS
MX4
Technology
Trinamic
TRINAMIC / ANALOG DEVICES
Trinamic Motion Control
Trinamic Motion Control GmbH

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