CH Vishay Sfernice 50 GHz Thin Film Microwave Resistors FEATURES SMD wraparound or flip chip resistor Small size, down to 20 mils by 16 mils Edged trimmed block resistors Pure alumina substrate (99.5 %) Various terminations: Pre-tinned over nickel barrier (wraparound (N) or flip chip (F)) for solder reflow Gold pad for wire (or ribbon) bonding (one face only) (P) and for glue attach (G) wraparound Ohmic range: 10R to 500R Design kits available -24 Small internal reactance (LC down to 1 10 ) Tolerance 1 %, 2 %, 5 %, 10 % TCR: 100 ppm/C in (- 55 C, + 155 C) temperature range Compliant to RoHS Directive 2002/95/EC Those miniaturized components are designed in such a way that their internal reactance is very small. When correctly mounted and utilized, they function as almost pure resistors on a very large range of frequency, up to 50 GHz. DIMENSIONS in millimeters (inches) A A D D D D C B C E E (F) and (P) (N) DIMENSIONS CASE SIZE AB C D/E POWER LIMITING MAX. TOL. RATING ELEMENT + 0.1 (+ 0.004) MAX. TOL. MAX. TOL. MAX. TOL. Pn VOLTAGE MIN. TOL. + 0.1 (+ 0.004) + 0.1 (+ 0.004) + 0.127 (+ 0.005) mW V - 0.1 (- 0.004) MIN. MAX. MIN. TOL. MIN. TOL. MIN. TOL. - 0.1 (- 0.004) - 0.1 (- 0.004) - 0.127 (- 0.005) (1) 02016 0.48 (0.020) 0.39 (0.016) 0.42 (0.02) 0.11 (0.004) 0.15 (0.008) 30 30 0402 1.00 (0.040) 0.6 (0.023) 0.5 (0.02) 0.15 (0.006) 0.35 (0.014) 50 37 0603 1.52 (0.060) 0.75 (0.030) 0.5 (0.02) 0.25 (0.010) 0.51 (0.020) 125 50 Note (1) + or - 0.07 mm ** Please see document Vishay Material Category Policy: www.vishay.com/doc 99902 www.vishay.com For technical questions, contact: sfer vishay.com Document Number: 53014 46 Revision: 29-Nov-10CH 50 GHz Thin Film Microwave Resistors Vishay Sfernice LAND PATTERN FLIP CHIP TERMINATIONS in millimeters G min. X max. Z max. CHIP SIZE Z X G max. max. min. 02016 0.53 0.44 0.15 0402 1.4 0.650 0.4 0603 1.71 0.9 0.760 Note Suggested land pattern: According to IPC-7351 Dimension and tolerance of land pattern shall be defined by PCB designer PCB can be designed according to IPC-7351A Generic Requirements for Surface Mount Design and Land Pattern Standard Example of land pattern: Fabrication allowance, assembly location and min. or max. level density board are not included in the exemple bellow. According to IPC-7351A Generic Requirements for Surface Mount Design and Land Pattern Standard: 2 2 2 Z = A + 2J + ()C ++F P with C: Unilateral profile tolerance for the component max. min. T A 2 2 2 G = F + 2J - ()C ++F P F: Unilateral profile tolerance for the board land pattern min. max. H F 2 2 2 X = B + 2J + ()C ++F P and P: Diameter of true position placement accuracy to the center of land pattern. max. min. S B For rectangular component Flip-Chip mounting, we suggest: J H J S J (TOE) 0 mm T J (HELL) 0 mm COMPONENT H J (SDE) 0 mm S J T Land Pattern Footprint WRAPAROUND TERMINATIONS in millimeters G min. Z max. CHIP SIZE Z G X max. min. max. 0402 1.55 0.15 0.73 0603 2.37 0.35 0.98 Document Number: 53014 For technical questions, contact: sfer vishay.com www.vishay.com Revision: 29-Nov-10 47 X max.