DATASHEET ICL7126 FN3084 Rev.5.00 3 1/2 Digit, Low Power, Single Chip A/D Converter Oct 25, 2004 The ICL7126 is a high performance, very low power Features 1 3 / -digit, A/D converter. All the necessary active devices 2 8,000 Hours Typical 9V Battery Life are contained on a single CMOS IC, including seven segment decoders, display drivers, reference, and clock. Guaranteed Zero Reading for 0V Input on All Scales The ICL7126 is designed to interface with a liquid crystal True Polarity at Zero for Precise Null Detection display (LCD) and includes a backplane drive. The supply 1pA Typical Input Current current of 100A is ideally suited for 9V battery operation. True Differential Input and Reference The ICL7126 brings together an unprecedented combination of high accuracy, versatility, and true economy. It features Direct LCD Display Drive - No External Components o auto-zero to less than 10V, zero drift of less than 1V/ C, Required input bias current of 10pA maximum, and rollover error of Pin Compatible With the ICL7106 less than one count. The versatility of true differential input and reference is useful in all systems, but gives the designer Low Noise - Less Than 15V P-P an uncommon advantage when measuring load cells, strain On-Chip Clock and Reference gauges and other bridge-type transducers. And finally the Low Power Dissipation Guaranteed Less Than 1mW true economy of single power operation allows a high performance panel meter or multi-meter to be built with the No Additional Active Circuits Required addition of only 10 passive components and a display. Pb-Free Available (RoHS Compliant) The ICL7126 can be used as a plug-in replacement for the ICL7106 in a wide variety of applications, changing only the Pinout passive components. ICL7126 (PDIP) TOP VIEW Ordering Information V+ 1 40 OSC 1 TEMP. RANGE PKG. 2 39 OSC 2 D1 PART NUMBER (C) PACKAGE DWG. C1 3 38 OSC 3 B1 4 37 TEST ICL7126CPL 0 to 70 40 Ld PDIP E40.6 (1s) 5 36 REF HI A1 ICL7126CPLZ 0 to 70 40 Ld PDIP E40.6 6 35 REF LO F1 (Note 1) (Pb-free) (Note 2) G1 7 34 C + REF NOTES: 8 33 C - E1 REF 1. Intersil Pb-free products employ special Pb-free material sets 9 32 COMMON D2 molding compounds/die attach materials and 100% matte tin C2 10 31 IN HI plate termination finish, which are RoHS compliant and 11 30 IN LO B2 compatible with both SnPb and Pb-free soldering operations. (10s) 12 29 A-Z A2 Intersil Pb-free products are MSL classified at Pb-free peak F2 13 28 BUFF reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. E2 14 27 INT 15 26 V- 2. Pb-free PDIPs can be used for through hole wave solder D3 processing only. They are not intended for use in Reflow solder B3 16 25 G2 (10s) (100s) processing applications. F3 17 24 C3 (100s) 18 23 A3 E3 (1000) AB4 19 22 G3 POL 20 21 BP/GND (MINUS) FN3084 Rev.5.00 Page 1 of 15 Oct 25, 2004ICL7126 Absolute Maximum Ratings Thermal Information o Supply Voltage V+ to V- . 15V Thermal Resistance (Typical, Note 2) ( C/W) JA Analog Input Voltage (Either Input) (Note 1) . V+ to V- PDIP Package . 50 o Reference Input Voltage (Either Input) . V+ to V- Maximum Junction Temperature .150 C o o Clock Input . TEST to V+ Maximum Storage Temperature Range -65 C to 150 C o Maximum Lead Temperature (Soldering 10s) .300 C Operating Conditions NOTE: Pb-free PDIPs can be used for through hole wave solder o o Temperature Range . 0 C to 70 C processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to 100 A. 2. is measured with the component mounted on an evaluation PC board in free air. JA o Electrical Specifications T = 25 C, V = 100mV, f = 48kHz (Notes 1, 3) A REF CLOCK PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Zero Input Reading V = 0.0V, Full Scale = 200mV -000.0 000.0 +000.0 Digital IN Reading Ratiometric Reading V = V , V = 100mV 999 999/100 1000 Digital lN REF REF 0 Reading Rollover Error -V = +V 200mV - 0.2 1 Counts IN lN Difference in Reading for Equal Positive and Negative Inputs Near Full Scale Linearity Full Scale = 200mV or Full Scale = 2V Maximum Deviation - 0.2 1 Counts from Best Straight Line Fit (Note 5) Common Mode Rejection Ratio V = 1V, V = 0V, Full Scale = 200mV (Note 5) - 50 - V/V CM IN Noise V = 0V, Full Scale = 200mV -15- V IN (Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5) Leakage Current Input V = 0V (Note 5) - 1 10 pA lN o o o Zero Reading Drift V = 0V, 0 C To 70 C (Note 5) - 0.2 1 V/ C lN o o o Scale Factor Temperature Coefficient V = 199mV, 0 C To 70 C, - 1 5 ppm/ C IN o (Ext. Ref. 0ppm/ C) (Note 5) V+ Supply Current V = 0V (Does Not Include COMMON Current) - 70 100 A IN COMMON Pin Analog Common Voltage 25k Between Common and Positive Supply 2.4 3.0 3.2 V (With Respect to + Supply) o Temperature Coefficient of Analog Common 25k Between Common and Positive Supply - 80 - ppm/ C (With Respect to + Supply) (Note 5) Peak-To-Peak Segment Drive Voltage V+ = to V- = 9V (Note 4) 4 5.5 6 V Peak-To-Peak Backplane Drive Voltage Power Dissipation Capacitance vs Clock Frequency - 40 - pF NOTES: 3. Unless otherwise noted, specifications are tested using the circuit of Figure 1. 4. Back plane drive is in phase with segment drive for off segment, 180 degrees out of phase for on segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design. FN3084 Rev.5.00 Page 2 of 15 Oct 25, 2004