HIGH-SPEED 7015L 8K x 9 DUAL-PORT STATIC RAM Features: M/S = VIH for BUSY output flag on Master True Dual-Ported memory cells which allow simultaneous M/S = VIL for BUSY input on Slave reads of the same memory location Busy and Interrupt Flag High-speed access On-chip port arbitration logic Commercial: 12ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT7015L Fully asynchronous operation from either port Active: 750mW (typ.) TTL-compatible, single 5V (10%) power supply Standby: 1mW (typ.) Available in 68-pin PLCC IDT7015 easily expands data bus width to 18 bits or more Green parts available, see ordering information using the Master/Slave select when cascading more than one device Functional Block Diagram OEL OER CER CEL R/WR R/WL I/O0L-I/O8L I/O0R-I/O8R I/O I/O Control Control (1,2) (1,2) BUSY BUSYR L A12L A12R Address MEMORY Address Decoder ARRAY Decoder A0R A0L 13 13 ARBITRATION CEL INTERRUPT CER SEMAPHORE OER OEL LOGIC R/WR R/WL SEML SEMR M/S (2) (2) INTL INTR 2954 drw 01 NOTES: 1. In MASTER mode: BUSY is an output and is a push-pull driver In SLAVE mode: BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers. MAY 2019 1 DSC 2954/137015L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range Description: The IDT7015 is a high-speed 8K x 9 Dual-Port Static RAM. The reads or writes to any location in memory. An automatic power down IDT7015 is designed to be used as a stand-alone Dual-Port RAM or as feature controlled by CE permits the on-chip circuitry of each port to enter a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more a very low standby power mode. word systems. Using the IDT MASTER/SLAVE Dual-Port RAM ap- Fabricated using CMOS high-performance technology, these proach in 18-bit or wider memory system applications results in full- devices typically operate on only 750mW of power. speed, error-free operation without the need for additional discrete logic. The IDT7015 is packaged in a 64-pin PLCC. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for (1,2,3) Pin Configurations 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 I/O7R 27 9 I/O1L I/O8R 28 8 I/O0L OER 29 7 I/O8L R/WR 30 6 OEL SEMR 31 5 R/WL CER 32 4 SEML 33 N/C 3 CEL N/C 34 2 N/C 35 GND 7015 1 N/C A12R 36 (4) PLG68 68 VCC 37 A11R 67 A12L A10R 38 66 A11L A9R 39 65 A10L A8R 40 64 A9L A7R 41 63 A8L 42 A6R 62 A7L 43 A5R 61 A6L 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2954 drw 02 Pin Names NOTES: Left Port Right Port Names 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. CEL CER Chip Enable 3. Package body is approximately .95 in x .95 in x .17 in. R/WL R/WR Read/Write Enable 4. This package code is used to reference the package diagram. OEL OER Output Enable A0L - A12L A0R - A12R Address I/O0L - I/O8L I/O0R - I/O8R Data Input/Output SEML SEMR Semaphore Enable Interrupt Flag INTL INTR BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 2954 tbl 01 6.422 A4R I/O6R A3R I/O5R A2R I/O4R A1R I/O3R A0R VCC INTR I/O2R BUSYR I/O1R M/S I/O0R GND GND BUSYL VCC INTL I/O7L A0L I/O6L A1L GND A2L I/O5L A3L I/O4L A4L I/O3L A5L I/O2L