NBVSBA018LN1TAG ON Semiconductor

NBVSBAXXX Series 2.5 V/3.3 V, LVPECL Voltage-Controlled Crystal Oscillator (VCXO) PureEdge Product Series NBVSBAXXX Series V CLK CLK DD 654 PLL Clock Multiplier 12 3 V OE GND C Figure 1. Simplified Logic Diagram V 1 6 V C DD OE 2 5 CLK GND 3 4 CLK Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION Pin No. Symbol I/O Description 1 V (Note 1) Analog Input Analog control voltage input pin that adjusts output oscillation frequency. f =V = 1.65 V C 0 C 2 OE LVTTL/LVCMOS Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. Control Input See OE pin description Table 2. 3 GND Power Supply Ground at 0 V. Electrical and Case Ground. 4 CLK LVPECL Output NonInverted Clock Output. Typically loaded with 50 receiver termination resistor to V = V 2 V. TT DD 5 CLK LVPECL Output Inverted Clock Output. Typically loaded with 50 receiver termination resistor to V = V 2 V. TT DD 6 V Power Supply Positive Power Supply Voltage. Voltage should not exceed 2.5 V 5% and 3.3 V 10%. DD 1. Control voltage has a positive slope with a linearity of 10% V = 1.65 V 1 V. C Table 2. OUTPUT ENABLE TRISTATE FUNCTION OE Pin Output Pins Open Active HIGH Level Active LOW Level High Z Table 3. ATTRIBUTES Characteristic Value Internal Default State Resistor 170 k ESD Protection Human Body Model 2 kV Machine Model 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.