MM74HC164 8-Bit Serial-in/Parallel-out Shift Register February 2008 MM74HC164 8-Bit Serial-in/Parallel-out Shift Register Features General Description Typical operating frequency: 50MHz The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low con- Typical propagation delay: 19ns (clock to Q) sumption of standard CMOS integrated circuits. It also Wide operating supply voltage range: 2V to 6V offers speeds comparable to low power Schottky Low input current: 1A maximum devices. Low quiescent supply current: 80A maximum This 8-bit shift register has gated serial inputs and (74HC Series) CLEAR. Each register bit is a D-type master/slave flip- Fanout of 10 LS-TTL loads flop. Inputs A & B permit complete control over the incoming data. A LOW at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high level on one input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only infor- mation meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V and ground. CC Ordering Information Package Order Number Number Package Description MM74HC164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC164MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC164 Rev. 1.5.0MM74HC164 8-Bit Serial-in/Parallel-out Shift Register Connection Diagram Truth Table Inputs Outputs Clear Clock A B Q Q ... Q A B H LX XX L L ... L HL XXQ Q ... Q AO BO HO H HH H Q ... Q An Gn H LX L Q ... Q A Gn H XL L Q ... Q An Gn H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) = Transition from LOW-to-HIGH level. Q , Q , Q = the level of Q , Q , or Q , AO BO HO A B H respectively, before the indicated steady state input conditions were established. Q , Q = The level of Q or Q before the most An Gn A G recent transition of the clock indicated a one-bit shift. Top View Logic Diagram 1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC164 Rev. 1.5.0 2