LPC82x 32-bit ARM Cortex-M0+ microcontroller up to 32 kB flash and 8 kB SRAM 12-bit ADC comparator Rev. 1.2 11 October 2016 Product data sheet 1. General description The LPC82x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC82x support up to 32 KB of flash memory and 8 KB of SRAM. 2 The peripheral complement of the LPC82x includes a CRC engine, four I C-bus interfaces, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self-wake-up timer, and state-configurable timer with PWM function (SCTimer/PWM), a DMA, one 12-bit ADC and one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 29 general-purpose I/O pins. For additional documentation related to the LPC82x parts, see Section 18. 2. Features and benefits System: ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port. ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). System tick timer. AHB multilayer matrix. Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported. MTB Memory: Up to 32 KB on-chip flash programming memory with 64 Byte page write and erase. Code Read Protection (CRP) supported. 8 KB SRAM. ROM API support: Boot loader. On-chip ROM APIs for ADC, SPI, I2C, USART, power configuration (power profiles) and integer divide. Flash In-Application Programming (IAP) and In-System Programming (ISP). Digital peripherals: High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 29 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and digital filter. GPIO direction control supports independent set/clear/toggle of individual bits. High-current source output driver (20 mA) on four pins.LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller High-current sink driver (20 mA) on two true open-drain pins. GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs. Switch matrix for flexible configuration of each I/O pin function. CRC engine. DMA with 18 channels and 9 trigger inputs. Timers: State Configurable Timer (SCTimer/PWM) with input and output functions (including capture and match) for timing and PWM applications. Each SCTimer/PWM input is multiplexed to allow selecting from several input sources such as pins, ADC interrupt, or comparator output. Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates. Self-Wake-up Timer (WKT) clocked from either the IRC, a low-power, low-frequency internal oscillator, or an external clock input in the always-on power domain. Windowed Watchdog timer (WWDT). Analog peripherals: One 12-bit ADC with up to 12 input channels with multiple internal and external trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports two independent conversion sequences. Comparator with four input pins and external or internal reference voltage. Serial peripherals: Three USART interfaces with pin functions assigned through the switch matrix and one common fractional baud rate generator. Two SPI controllers with pin functions assigned through the switch matrix. 2 Four I C-bus interfaces. One I2C supports Fast-mode Plus with 1 Mbit/s data rates on two true open-drain pins and listen mode. Three I2Cs support data rates up to 400 kbit/s on standard digital pins. Clock generation: 12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be used as a system clock. Crystal oscillator with an operating range of 1 MHz to 25 MHz. Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator, the external clock input, or the internal RC oscillator. Clock output function with divider that can reflect all internal clock sources. Power control: Power consumption in active mode as low as 90 uA/MHz in low-current mode using the IRC as the clock source. Integrated PMU (Power Management Unit) to minimize power consumption. Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI, and I2C peripherals. Timer-controlled self wake-up from Deep power-down mode. LPC82x All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 1.2 11 October 2016 2 of 82