74LVC161PW,118

74LVC161 Presettable synchronous 4-bit binary counter asynchronous reset Rev. 7 22 September 2021 Product data sheet 1. General description The 74LVC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. 2. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power dissipation Direct interface with TTL levels Asynchronous reset Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 CNexperia 74LVC161 Presettable synchronous 4-bit binary counter asynchronous reset 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC161D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LVC161PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74LVC161BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 4. Functional diagram 1 CTR4 R 9 M1 15 7 G3 10 TC G4 2 3 D0 Q0 14 C2/1,3,4+ 13 4 D1 Q1 14 3 1,2D 12 5 D2 Q2 13 4 6 D3 Q3 11 12 5 9 PE 6 11 CEP CET CP MR 15 4 CT = 15 mna905 7 10 2 1 mna906 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 3 4 5 6 D0 D1 D2 D3 PE PARALLEL LOAD 0 1 2 3 4 9 CIRCUITRY CET 10 15 5 TC 15 CEP 7 14 6 BINARY CP 2 COUNTER MR 1 13 7 Q0 Q1 Q2 Q3 12 11 10 9 8 mna907 14 13 12 11 mna908 Fig. 3. Functional diagram Fig. 4. State diagram 74LVC161 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 7 22 September 2021 2 / 19