74AHC1G79GV,125

74AHC1G79 74AHCT1G79 Single D-type flip-flop positive-edge trigger Rev. 8 11 January 2022 Product data sheet 1. General description The 74AHC1G79 74AHCT1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits Wide supply voltage range from 2.0 to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Symmetrical output impedance Balanced propagation delays Input levels: For 74AHC1G79: CMOS level For 74AHCT1G79: TTL level ESD protection: HBM JESD22-A114F: exceeds 2000 V MM JESD22-A115-A: exceeds 200 V CDM JESD22-C101C: exceeds 1000 V Specified from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC1G79GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74AHCT1G79GW 74AHC1G79GV -40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74AHCT1G79GVNexperia 74AHC1G79 74AHCT1G79 Single D-type flip-flop positive-edge trigger 4. Marking Table 2. Marking codes Type number Marking 1 74AHC1G79GW AP 74AHCT1G79GW CP 74AHC1G79GV A79 74AHCT1G79GV C79 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 D Q 4 1 4 D Q 2 2 CP CP mna440 mna441 Fig. 1. Logic symbol Fig. 2. IEC logic symbol CP C C C C D TG TG Q C C C C TG TG C C mna442 Fig. 3. Logic diagram 74AHC AHCT1G79 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 8 11 January 2022 2 / 12