SY58611U 3.2Gbps Precision, LVDS 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58611U is a 2.5V, high-speed, fully differential Precision Edge LVDS 2:1 MUX capable of processing clocks up to Features 2.5GHz and data up to 3.2Gbps. SY58611U is Selects between two sources and provides buffered optimized to provide a buffered output of the selected copy of the selected input signal input with less than 20ps of skew and less than 10ps pp total jitter. Patented MUX Isolation design reduces Fail Safe Input crosstalk and provides superior signal integrity. Prevents output from oscillating when input is invalid or removed The differential inputs include Micrels unique, 3-pin input termination architecture that interfaces to LVPECL, Guaranteed AC performance over temperature and LVDS or CML differential signals, (AC- or DC-coupled) voltage: as small as 100mV (200mV ) without any level- PK pp DC-to > 3.2Gbps throughput shifting or termination resistor networks in the signal <420ps typical propagation delay (IN-to-Q) path. For AC-coupled input interface applications, an <120ps rise/fall times integrated reference voltage (V ) is provided to bias REF-AC Unique, patented internal termination and VT pin the V pin. The output is LVDS compatible, with rise/fall T accepts DC- and AC-coupled inputs (CML, PECL, times guaranteed to be less than 120ps. LVDS) The SY58611U operates from a 2.5V 5% supply and is Unique, patented MUX input isolation design guaranteed over the full industrial temperature range minimizes adjacent channel crosstalk (40C to +85C). For applications that require CML or Ultra-low jitter design LVPECL output, consider the SY58609U and SY58610U, 2:1 MUX with 400mV and 800mV output <1ps cycle-to-cycle jitter RMS swings respectively. The SY58611U is part of Micrels <10ps total jitter PP high-speed, Precision Edge product line. <1ps random jitter RMS Datasheets and support documentation can be found on <10ps deterministic jitter PP Micrels web site at: www.micrel.com. 2.5V 5% power supply operation Industrial temperature range: 40C to +85C Functional Block Diagram Available in 16-pin (3mm x 3mm) QFN package Applications All SONET clock distribution Fibre Channel clock and data distribution Gigabit Ethernet clock or data distribution Backplane distribution Markets DataCom and Telecom Storage ATE Test and Measurement United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY58611U (1) Ordering Information Part Number Package Operating Package Marking Lead Type Range Finish SY58611UMG QFN-16 Industrial 611U with Pb-Free NiPdAu bar-line indicator Pb-Free (2) SY58611UMGTR QFN-16 Industrial 611U with Pb-Free NiPdAu bar-line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. Pin Configuration Truth Table SEL Output 0 IN0 Selected 1 IN1 Selected 16-Pin QFN Pin Description Pin Number Pin Name Pin Function 1, 4 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See Input Interface Applications subsection. 2, 3 VREF-AC0, Reference Voltage: These outputs bias to V 1.2V. They are used for AC-coupling inputs IN CC VREF-AC1 and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is 0.5mA. See Input Interface Applications subsection. 5, 6 IN1, /IN1 Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-Coupled differential signals as small as 100mV (200mV ). Each pin of the PP 15, 16 IN0, /IN0 pairs internally terminates with 50 to the V pin. If the input swing falls below a certain T threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See Input Interface Applications subsection. 7 SEL Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is V /2. CC 8, 13 VCC Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the V pins CC as possible. 9, 12 /Q, Q LVDS Differential Output Pair: Differential buffered output copy of the selected input signal. The output swing is typically 325mV. Normally terminated 100 across the output (Q and /Q). See LVDS Output Interface Applications subsection. 10, 11 GND, Ground. Exposed pad must be connected to a ground plane that is the same potential as the Exposed pad ground pin. 14 NC No connect. 2 M9999-030607-A March 2007 hbwhelp micrel.com or (408) 955-1690