TM
CMOS ST-BUS Family MT8986
Multiple Rate Digital Switch
Data Sheet
September 2011
Features
256 x 256 or 512 x 256 switching configurations Ordering Information
8-bit or 4-bit channel switching capability MT8986AP1 44 Pin PLCC* Tubes
MT8986APR1 44 Pin PLCC* Tape & Reel
Guarantees frame integrity for wideband
MT8986AL1 44 Pin MQFP* Trays
channels MT8986AE1 40 Pin PDIP* Tubes
*Pb Free Matte Tin
Automatic identification of ST-BUS/GCI interfaces
-40 C to +85 C
Accepts serial streams with data rates up to
8.192 Mb/s
Rate conversion from 2.048 Mb/s to 4.096 or
Description
8.192 Mb/s and vice-versa
Programmable frame offset on inputs
The Multiple Rate Digital Switch (MRDX) is an
upgraded version of Zarlink's MT8980D Digital Switch
Per-channel three-state control
(DX). It is pin compatible with the MT8980D and
Per-channel message mode
retains all of its functionality. This device is designed to
Control interface compatible to Intel/Motorola
provide simultaneous connections (non-blocking) for
CPUs
up to 256 64 kb/s channels or blocking connections for
Low power consumption
up to 512 64kb/s channels. The serial inputs and
outputs connected to MT8986 may have 32 to 128
Applications
64 kb/s channels per frame with data rates ranging
from 2048 up to 8192 kb/s. The MT8986 provides per-
Medium size digital switch matrices
channel selection between variable and constant
Hyperchannel switching (e.g., ISDN H0)
throughput delays allowing voice and grouped data
MVIP interface functions
channels to be switched without corrupting the data
Serial bus control and monitoring
sequence integrity.
Centralized voice processing systems
Voice/Data multiplexer
In addition, the MT8986 can be used for switching of
32 kbit/s channel switching
32 kb/s channels in ADPCM applications. The MT8986
is ideal for medium size mixed voice and data
switching/processing applications.
V V ODE
DD SS
STi0
Output
STi1 STo0
Multiple Buffer Data MUX
STi2
STo1
STi3 Memory
Serial
STi4 STo2
Parallel
STi5
to
to
STo3
STi6
Parallel
Serial
STi7 STo4
Converter
Internal Registers
Converter
STi8
STo5
Timing
STi9
Connection
*STi10 Unit
STo6
*STi11 Memory
STo7
*STi12
*STi13
STo8 *
*STi14 Microprocessor
STo9 *
*STi15
Interface
CLK FR AS/ IM DS A0/ AD7/ CSTo
CS R/W DTA
* 44 Pin only
ALE * A7 AD0
RD
WR
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.MT8986 Data Sheet
Change Summary
Changes from the November 2005 issue to the September 2011 issue.
Page Item Change
1 Ordering Information Removed leaded packages as per PCN notice.
654 32 144434241 40
STi3 7 39 STo3
1 33
STi3
STo3
8 38
STi4 STo4 2
32
STi4
STo4
9
37 STo5
STi5 3
31
STi5
STo5
10
STi6/A6 36 STo6/A6
4
STi6/A6 30
STo6/A6
11
STi7/A7 35 STo7/A7
5 29
STi7/A7
STo7/A7
12
VDD 34 VSS
6
VDD 28
VSS
13
FR 33 AD0
7
FR 27
AD0
CLK 14 32 AD1
8
CLK 26 AD1
STi8/A0 15 31
AD2
STi8/A0 9 25
AD2
16 30
STi9/A1 AD3
STi9/A1 10 24 AD3
29
STi10/A2 AD4
17
11
STi10/A2 23 AD4
18 19 20 21 22 23 24 25 26 27 28
44 PIN PLCC 44 PIN QFP
1 40
CSTo
DTA
2 39
STi0 ODE
3 38 STo0
STi1
4 37 STo1
STi2
5
36 STo2
STi3
6 35 STo3
STi4
7 34 STo4
STi5
8 33 STo5
STi6/A6
9 32 STo6/A6
STi7/A7
10 31 STo7/A7
VDD
11 30 VSS
FR
12 29 AD0
CLK
A0 13 28 AD1
A1 14 27 AD2
A2 15 26 AD3
A3 16 25 AD4
A4 17 24
AD5
A5 18 23
AD6
DS/RD 19 22
AD7
R/W\WR 20 21
CS
40 PIN DIP
Figure 2 - Pin Connections
2
Zarlink Semiconductor Inc.
AS/ALE
IM
STi2
STi11/A3
STi1
STi12/A4
STi0
STi3/A5
DTA
DS/RD
CSTo
R/W/WR
ODE
CS
STo0
AD7
STo1
AD6
STo2
AD5
STi4/STo8
STi15/STo9
44
IM 12 AS/ALE
13 43
STi11/A3 STi2
STi12/A4
14 42 STi1
STi3/A5
41 STi0
15
DS/RD
16 40 DTA
R/W/WR
17 39 CSTo
CS
18 38 ODE
AD7
19 37 STo0
AD6
36 STo1
20
AD5
35 STo2
21
STi15/STo9
34 STi4/STo8
22