GS72116AGP/U
7, 8, 10, 12 ns
TSOP, FP-BGA
128K x 16
3.3 V V
DD
Commercial Temp
2Mb Asynchronous SRAM Center V and V
Industrial Temp
DD SS
Features Fine Pitch BGA 128K x 16-Bump Configuration
Fast access time: 7, 8, 10, 12 ns
1 2 3 4 5 6
CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
Single 3.3 V power supply
LB OE A0 A1 A2 NC
A
All inputs and outputs are TTL-compatible
Byte control
B DQ16 UB A3 A4 CE DQ1
Fully static operation
Industrial Temperature Option: 40 to 85C
C DQ14 DQ15 A5 A6 DQ2 DQ3
Package line up
V V
D DQ13 NC A7 DQ4
SS DD
GP: RoHS-compliant 400 mil, 44-pin TSOP Type II
package
V V
E DQ12 NC A16 DQ5
DD SS
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid
F DQ11 DQ10 A8 A9 DQ7 DQ6
Array package
G DQ9 NC A10 A11 WE DQ8
Description
H NC A12 A13 A14 A15 NC
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
6 mm x 8 mm, 0.75 mm Bump Pitch
single 3.3 V power supply and all inputs and outputs are TTL-
Top View
compatible. The GS72116A is available in a 6 mm x 8 mm
Package U
Fine Pitch BGA and 400 mil TSOP Type-II packages.
TSOP-II 128K x 16-Pin Configuration
44
A4 1 A5
Pin Descriptions
43
A3 2 A6
42
3
A2 A7
Symbol Description
41
4
A1 OE
Top view
40
5
A0 UB
A0A16 Address input
39
CE 6 LB
DQ1DQ16 Data input/output
38
DQ1 7 DQ16
37
DQ2 8 DQ15
CE Chip enable input
36
9
DQ3 DQ14
Lower byte enable input
35
10
DQ4
LB
DQ13
44-pin
(DQ1 to DQ8)
34
11
V
DD
V
SS
33
12
Upper byte enable input
V
V
SS
DD
UB
TSOP II
32
13
(DQ9 to DQ16)
DQ5 DQ12
31
14
DQ6 DQ11
WE Write enable input
30
15
DQ7 DQ10
OE Output enable input 29
16
DQ8 DQ9
28
17
WE NC
V
+3.3 V power supply
DD
27
18
A15 A8
V
Ground 26
A14 19 A9
SS
25
20
A13 A10
NC No connect
21 24
A11
A12
22 23
A16 NC
Package TP
Rev: 1.11 1/2013 1/13 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see GS72116AGP/U
Block Diagram
A0
Row
Memory Array
Decoder
Address
Input
Buffer
Column
A16 Decoder
CE
WE
I/O Buffer
Control
OE
_____
UB
DQ16
DQ1
Truth Table
CE OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 VDD Current
H X X X X Not Selected Not Selected ISB1, ISB2
L L Read Read
L L H L H Read High Z
H L High Z Read
L L Write Write
IDD
L X L L H Write Not Write, High Z
H L Not Write, High Z Write
L H H X X High Z High Z
L X X H H High Z High Z
Note:
X: H or L
Rev: 1.11 1/2013 2/13 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see