ATF-531P8
[1]
High Linearity Enhancement Mode Pseudomorphic HEMT
2 [3]
in 2x2 mm LPCC Package
Data Sheet
Description Features
Single voltage operation
Avago Technologies ATF531P8 is a single voltage high
linearity, low noise EpHEMT housed in an 8lead JEDEC
High linearity and gain
[3]
standard leadless plastic chip carrier (LPCC ) package.
Low noise figure
The device is ideal as a high linearity, lownoise , medium
Excellent uniformity in product specifications
power amplifier. Its operating frequency range is from 50
MHz to 6 GHz.
Small package size:
2.0 x 2.0 x 0.75 mm
The thermally efficient package measures only 2 mm
[2]
x 2 mm x 0.75 mm. Its backside metalization provides Point MTTF > 300 years
excellent thermal dissipation as well as visual evidence
MSL1 and leadfr ee
of solder reflow. The device has a Point MTTF of over 300
Tapeandreel packaging option available
years at a mounting temperature of +85C. All devices are
100% RF & DC tested.
Specifications
Pin Connections and Package Marking
2 GHz; 4V, 135 mA (Typ.)
38 dBm output IP3
Pin 8 Pin 1 (Source)
0.6 dB noise figure
Pin 7 (Drain) Pin 2 (Gate)
20 dB gain
Pin 6 Pin 3
[4]
10.7 dB LFOM
Pin 5 Pin 4 (Source)
24.5 dBm output power at 1 dB gain compression
Bottom View
Applications
Pin 1 (Source) Pin 8
Front end LNA Q1 and Q2 driver or pre driver ampli
fier for Cellular/PCS and WCDMA wireless infrastruc
Pin 2 (Gate) Pin 7 (Drain)
3Px ture
Pin 3 Pin 6
Driver amplifier for WLAN, WLL/RLL and MMDS ap
Pin 4 (Source) Pin 5
plications
Top View
General purpose discrete EpHEMT for other high
linearity applications
Note:
Package marking provides orientation and identification:
3P = Device Code
x = Date code indicates the month of manufacture.
Notes:
1. Enhancement mode technology employs a single positive V , eliminating the need of negative gate voltage associated with conventional
gs
depletion mode devices.
2. Refer to reliability datasheet for detailed MTTF data.
3. Conforms to JEDEC reference outline MO229 for DRPN
4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC bias power.
Source
(Thermal/RF Gnd)[1]
ATF-531P8 Absolute Maximum Ratings
Notes:
Absolute
1. Operation of this device in excess of any one
Symbol Parameter Units Maximum
of these parameters may cause permanent
[2]
damage.
V DrainSource Voltage V 7
DS
2. Assumes DC quiescent conditions.
[2]
V GateSource Voltage V 7 t o 1
GS 3. Board (package belly) temperatureT is 25C.
B
[2] Derate 16 mW/C for T > 87C.
V Gate Drain Voltage V 7 t o 1 B
GD
4. Thermal resistance measured using
[2]
I Drain Current mA 300
150C Liquid Crystal Measurement meth
DS
od.
I Gate Current mA 20
GS
5. Device can safely handle +24 dBm RF Input
[3]
Power provided IGS is limited to 20mA. IGS
P Total Power Dissipation W 1
diss
at P1dB drive level is bias circuit depen
P RF Input Power dBm +24
in max.
dent.
T Channel Temperature C 150
CH
T Storage Temperature C 65 to 150
STG
[4]
Thermal Resistance C/W 63
ch_b
[5,6]
Product Consistency Distribution Charts at GHz, 4V, 135 mA
160
180
400
Cpk = 1.2
Cpk = 1.0
0.9 V
150 Stdev = 0.71
Stdev = 0.14
120
300
0.8 V 120
-3 Std +3 Std -3 Std +3 Std
90 80
200
0.7 V
60
40
100
0.6 V
30
0.5 V
0 0
0
35 36 37 38 39 40 41
0 0.3 0.6 0.9 1.2
0 1 2 3 4 5 6 7
NF (dB) OIP3 (dBm)
V (V)
DS
Figure 2. NF Figure 3. OIP3
Figure 1. Typical I-V Curves
LSL = 35.5, Nominal = 38.1.
Nominal = 0.6, USL = 1.0.
(V = 0.1 per step).
gs
300
240
Cpk = 2.0
Stdev = 0.12
250 200
Stdev = 0.21
200 160
-3 Std +3 Std -3 Std +3 Std
150 120
100 80
50
40
0 0
18.5 19.5 20.5 21.5 24.6
24.2 24.4 24.8 25 25.2
GAIN (dB) P1dB (dBm)
Figure 4. Small Signal Gain Figure 5. P1dB
LSL = 18.5, Nominal = 20.2 dB, USL = 21.5. Nominal = 24.6.
Notes:
5. Distribution data sample size is 500 samples taken from 5 different wafers and 3 different lots. Future wafers allocated to this product may
have nominal values anywhere between the upper and lower limits.
6. Measurements are made on production test board, which represents a trade off between optimal OIP3, NF and VSWR. Circuit losses have
been deembedded from actual measurements.
I (mA)
DS