X-On Electronics has gained recognition as a prominent supplier of ADF4212LBRUZ-RL7 phase locked loops - pll across the USA, India, Europe, Australia, and various other global locations. ADF4212LBRUZ-RL7 phase locked loops - pll are a product manufactured by Analog Devices. We provide cost-effective solutions for phase locked loops - pll, ensuring timely deliveries around the world.

ADF4212LBRUZ-RL7 Analog Devices

ADF4212LBRUZ-RL7 electronic component of Analog Devices
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Part No.ADF4212LBRUZ-RL7
Manufacturer: Analog Devices
Category:Phase Locked Loops - PLL
Description: Phase Locked Loops - PLL Dual Power Freq Synthesizer
Datasheet: ADF4212LBRUZ-RL7 Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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500 : USD 6.1
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Dual Low Power PLL Frequency Synthesizer Data Sheet ADF4212L FEATURES GENERAL DESCRIPTION I total: 7.5 mA The ADF4212L is a dual frequency synthesizer that can be used DD Bandwidth RF/IF: 2.4 GHz/1.0 GHz to implement local oscillators (LO) in the up-conversion and 2.7 V to 3.3 V power supply down-conversion sections of wireless receivers and transmitters. Separate V allows extended tuning voltage P It can provide the LO for both the RF and IF sections. It consists Programmable dual modulus prescaler of a low noise digital phase frequency detector (PFD), a precision RF and IF: 8/9, 16/17, 32/33, 64/65 charge pump, a programmable reference divider, programmable Programmable charge pump currents A and B counters, and a dual modulus prescaler (P/P + 1). The 3-wire serial interface A (6-bit) and B (12-bit) counters, in conjunction with the dual Analog and digital lock detect modulus prescaler (P/P + 1), implement an N divider (N = BP + Fastlock mode A). In addition, the 15-bit reference counter (R counter) allows Power-down mode selectable REFIN frequencies at the PFD input. A complete phase- 20-lead TSSOP and 20-lead LFCSP packages locked loop (PLL) can be implemented if the synthesizer is used with external loop filters and voltage controlled oscillators (VCOs). APPLICATIONS Control of all the on-chip registers is via a simple 3-wire Wireless handsets (GSM, PCS, DCS, DSC1800, CDMA, interface with 1.8 V compatibility. The devices operate with a WCDMA) power supply ranging from 2.7 V to 3.3 V and can be powered Base stations for wireless Radio (GSM, PCS, DCS, down when not in use. CDMA, WCDMA) Wireless LANS Cable TV tuners (CATV) Communications test equipment FUNCTIONAL BLOCK DIAGRAM V 1 V 2 V 1 V 2 R DD DD P P SET ADF4212L IF PHASE FREQUENCY REFERENCE DETECTOR 12-BIT IF B-COUNTER CHARGE CP IF PUMP IF IN IF PRESCALER 6-BIT IF IF CURRENT A-COUNTER SETTING IF LOCK DETECT IFCP3 IFCP2 IFCP1 REF OSCILLATOR IN 15-BIT IF R-COUNTER OUTPUT MUXOUT CLK MUX 22-BIT DATA DATA SDOUT REGISTER LE RFCP3 RFCP2 RFCP1 RF 15-BIT RF LOCK R-COUNTER DETECT REFERENCE CHARGE 12-BIT RF CP RF PUMP B-COUNTER RF IN RF RF PHASE PRESCALER FREQUENCY REFERENCE DETECTOR 6-BIT RF R A-COUNTER SET FL SWITCH O FL O DGND AGND DGND AGND RF RF IF IF Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20022014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 02774-001ADF4212L Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MUXOUT and Lock Detect ...................................................... 14 Applications ....................................................................................... 1 Lock Detect ................................................................................. 14 General Description ......................................................................... 1 RF/IF Input Shift Register ......................................................... 14 Functional Block Diagram .............................................................. 1 IF R Counter Latch ..................................................................... 16 Revision History ............................................................................... 2 IF N Counter Latch .................................................................... 17 Specifications ..................................................................................... 3 RF R Counter Latch ................................................................... 18 Timing Characteristics ................................................................ 5 RF N Counter Latch ................................................................... 19 Absolute Maximum Ratings ............................................................ 6 Program Modes .............................................................................. 20 ESD Caution .................................................................................. 6 IF and RF Power-Down ............................................................. 20 Pin Configurations and Function Descriptions ........................... 7 IF Section ..................................................................................... 20 Typical Performance Characteristics ............................................. 9 RF Section ................................................................................... 21 Circuit Description ......................................................................... 13 Applications Information .............................................................. 22 Reference Input Section ............................................................. 13 Local Oscillator for GSM Handset Receiver ............................... 22 RF/IF Input Stage........................................................................ 13 Wideband PLL ............................................................................ 23 Prescaler (P/P + 1) ...................................................................... 13 Interfacing ................................................................................... 24 RF/IF A and B Counters ............................................................ 13 PCB Design Guidelines for Lead Frame Chip Scale Package ..................................................................... 24 Pulse Swallow Function ............................................................. 13 Outline Dimensions ....................................................................... 25 RF/IF R Counter ......................................................................... 13 Ordering Guide .......................................................................... 26 Phase Frequency Detector (PFD) and Charge Pump ............ 14 REVISION HISTORY 1/14Rev. D to Rev. E Changes to RF/IF Input Shift Register Section ........................... 14 Changes to Table 10 ........................................................................ 18 Changes to Programmable IF Reference (R) Counter Section, IF Program Modes Section, and IF Power-Down Section ........ 20 8/12Rev. C to Rev D Changes to Programmable RF Reference (R) Counter Section, Changed CP-20-1 to CP-20-6 ........................................... Universal RF Program Modes Section, Programmable RF N Counter Updated Outline Dimensions ....................................................... 25 Section, and RF Power-Down Section ......................................... 21 Changes to Ordering Guide .......................................................... 26 Changes to Figure 32 ...................................................................... 23 Changes to Figure 33 and Figure 34............................................. 24 11/10Rev. B to Rev C Added PCB Design Guidelines for Lead Frame Chip Scale Changes to VP1, VP2 to GND Parameter, Table 4 and VP1, VP2 Package Section............................................................................... 24 to V 1, V 2 Parameter, Table 4 ................................................... 6 Updated Outline Dimensions ....................................................... 25 DD DD Changes to Ordering Guide .......................................................... 26 Changes to Ordering Guide .......................................................... 25 9/08Rev. A to Rev B 3/03Data Sheet changed from REV. 0 to REV. A Updated Format .................................................................. Universal Changes to General Description ..................................................... 1 Changes to Figure 1 and General Description Section ............... 1 Changes to Specifications ................................................................. 3 Changes to Prescaler Output Frequency Parameter and RF Changes to Table 9 .......................................................................... 18 Input Frequency (RFIN) Parameter ................................................. 3 Changes to Table 11 ....................................................................... 20 Changes to Table 3 and Figure 2 ..................................................... 5 Changes to Figure 31 ...................................................................... 23 Changes to Figure 4 .......................................................................... 7 Changes to Figure 27, RF/IF A and B Counters Section, Pulse 11/02Revision 0: Initial Version Swallow Function Section, and RF/IF R Counter Section ........ 13 Rev. E Page 2 of 28

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