2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec Data Sheet ADAU1328 FEATURES GENERAL DESCRIPTION PLL generated or direct master clock The ADAU1328 is a high performance, single-chip codec that Low EMI design provides two analog-to-digital converters (ADCs) with differential 108 dB DAC/107 dB ADC dynamic range and SNR input and eight digital-to-analog converters (DACs) with 94 dB THD + N single-ended output using the Analog Devices, Inc. patented Single 3.3 V supply multibit sigma-delta (-) architecture. An SPI port is included, Tolerance for 5 V logic inputs allowing a microcontroller to adjust volume and many other Supports 24 bits and 8 kHz to 192 kHz sample rates parameters. The ADAU1328 operates from 3.3 V digital and Differential ADC input analog supplies. The ADAU1328 is available in a 48-lead Single-ended DAC output (single-ended output) LQFP. Other members of this family Log volume control with autoramp function include a differential DAC output version. SPI controllable for flexibility The ADAU1328 is designed for low EMI. This consideration is Software controllable clickless mute apparent in both the system and circuit design architectures. Software power-down 2 By using the on-board PLL to derive the master clock from the Right justified, left justified, I S and TDM modes LR clock or from an external crystal, the ADAU1328 eliminates Master and slave modes up to 16-channel in/out the need for a separate high frequency master clock and can 48-lead LQFP also be used with a suppressed bit clock. The digital-to-analog and analog-to-digital converters are designed using the latest APPLICATIONS ADI continuous time architectures to further minimize EMI. By Home theater systems using 3.3 V supplies, power consumption is minimized, further Set-top boxes reducing emissions. Digital audio effects processors FUNCTIONAL BLOCK DIAGRAM DIGITAL AUDIO INPUT/OUTPUT ADAU1328 SERIAL DATA PORT DAC DAC SDATA SDATA DAC OUT IN DIGITAL ADC CLOCKS FILTER DAC DEC AND FILTER VOLUME DAC 48/96/ ADC CONTROL TIMING MANAGEMENT 192kHz AND CONTROL DAC (CLOCK AND PLL) DAC DAC CONTROL PORT PRECISION SPI VOLTAGE 12.488MHz 6.144MHz REFERENCE CONTROL DATA INPUT/OUTPUT Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2006-2013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 06102-001ADAU1328 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog-to-Digital Converters (ADCs) .................................... 13 Applications ....................................................................................... 1 Digital-to-Analog Converters (DACs) .................................... 13 General Description ......................................................................... 1 Clock Signals ............................................................................... 13 Functional Block Diagram .............................................................. 1 Reset and Power-Down ............................................................. 14 Revision History ............................................................................... 2 Serial Control Port ..................................................................... 14 Specifications ..................................................................................... 3 Power Supply and Voltage Reference ....................................... 15 Test Conditions ............................................................................. 3 Serial Data PortsData Format ............................................... 15 Analog Performance Specifications ........................................... 3 Time-Division Multiplexed (TDM) Modes ............................ 15 Crystal Oscillator Specifications................................................. 4 Daisy-Chain Mode ..................................................................... 19 Digital Input/Output Specifications........................................... 4 Control Registers ............................................................................ 24 Power Supply Specifications........................................................ 5 Definitions ................................................................................... 24 Digital Filters ................................................................................. 6 PLL and Clock Control Registers ............................................. 24 Timing Specifications .................................................................. 6 DAC Control Registers .............................................................. 25 Absolute Maximum Ratings ............................................................ 8 ADC Control Registers .............................................................. 27 Thermal Resistance ...................................................................... 8 Additional Modes ....................................................................... 29 ESD Caution .................................................................................. 8 Application Circuits ....................................................................... 30 Pin Configuration and Function Descriptions ............................. 9 Outline Dimensions ....................................................................... 31 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 31 Theory of Operation ...................................................................... 13 REVISION HISTORY 2/13Rev. A to Rev. B Changes to tCLH Parameter, Comments Column, Table 6............ 7 Changes to Serial Control Port Section ....................................... 14 7/11Rev. 0 to Rev. A 2 Deleted References to I C ............................................. Throughout Changes to Table 9, DSDATAx/ASDATAx Pin Descriptions ..... 9 Updated Outline Dimensions ....................................................... 31 6/06Revision 0: Initial Version Rev. B Page 2 of 32