AS4C64M16MD2-25BCN AS4C32M32MD2-25BCN Revision History AS4C64M16MD2-25BCN / AS4C32M32MD2-25BCN 134 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet July. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/129 - Rev.1.0 July 2016AS4C64M16MD2-25BCN AS4C32M32MD2-25BCN KEY FEATURE Double-data rate architecture two data transfers per clock cycle Bidirectional data strobes (DQS, DQS ), These are transmitted/received with data to be used in capturing data at the receiver Differential clock inputs (CK and CK ) Differential data strobes (DQS and DQS ) Commands & addresses entered on both positive and negative CK edges data and data mask referenced to both edges of DQS 8 internal banks for concurrent operation Data mask (DM) for write data Burst Length: 4 (default), 8 or 16 Burst Type: Sequential or Interleave Read & Write latency : Refer to Table 47 Auto Precharge option for each burst access Configurable Drive Strength Auto Refresh and Self Refresh Modes Partial Array Self Refresh and Temperature Compensated Self Refresh Deep Power Down Mode HSUL 12 compatible inputs VDD1/VDD2/VDDQ : 1.8V/1.2V/1.2V No DLL : CK to DQS is not synchronized Edge aligned data output, center aligned data input Auto refresh duty cycle : - 7.8us for -30 to 85 C Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package AS4C 64M16MD2-25BCN 400 134-ball FBGA 64Mx16 Commercial -30C to + 85C AS4C32M32MD2-25BCN 134-ball FBGA 32Mx32 400 Commercial -30C to +85C Table 2. Speed Grade Information Speed Grade Clock Frequency tRCD (ns) tRP (ns) RL WL DDR2L-800 18 18 6 400MHz 3 Confidential - 2/129 - Rev.1.0 July 2016