AS4C4M32S 4M x 32 bit Synchronous DRAM (SDRAM) Alliance Memory Confidential (Rev.3.0, May. /2014) Features Table 1. Key Specifications Clock rate: 143/166 MHz AS4C4M32S -6/7 Fully synchronous operation tCK3 Clock Cycle time(min.) 6/7ns Internal pipelined architecture tAC3 Access time from CLK (max.) 5.5 ns 1M word x 32-bit x 4-bank Programmable Mode tRAS Row Active time(min.) 42 ns - CAS Latency: 2, or 3 tRC Row Cycle time(min.) 60 ns - Burst Length: 1, 2, 4, 8, or full page Table 2. Ordering Information - Burst Type: Sequential & Interleave - Burst-Read-Single-Write Part Number Frequency Package - Burst stop function AS4C4M32S-7TCN 143MHz 86 pin TSOP II Individual byte controlled by DQM0-3 AS4C4M32S-6TCN 166MHz 86 pin TSOP II Operating temperature range Commercial (0 ~ 70C) AS4C4M32S-6TIN 166MHz 86 pin TSOP II T: indicates TSOP II package Industrial (-40 ~ 85C) C: indicates Commercial temp. I: indicates Industrial temp Auto Refresh and Self Refresh N: indicates lead free 4096 refresh cycles/64ms Single 3.3V power supply Figure 1. Pin Assignment (Top View) Interface: LVTTL 86-pin 400 mil plastic TSOP II VDD 1 86 VSS DQ0 2 85 DQ15 package - Pb free and Halogen free VDDQ 3 84 VSSQ DQ1 4 83 DQ14 DQ2 5 82 DQ13 VSSQ 6 81 VDDQ Overview DQ3 7 80 DQ12 DQ4 8 79 DQ11 The AS4C4M32S SDRAM is a high-speed VDDQ 9 78 VSSQ CMOS synchronous DRAM containing 128 Mbits. It is DQ5 10 77 DQ10 internally configured as a quad 1M x 32 DRAM with a DQ6 11 76 DQ9 VSSQ 12 75 VDDQ synchronous interface (all signals are registered on DQ7 13 74 DQ8 the positive edge of the clock signal, CLK). Each of NC 14 73 NC the 1M x 32 bit banks is organized as 4096 rows by VDD 15 72 VSS DQM0 16 71 DQM1 256 columns by 32 bits. Read and write accesses to WE 17 70 NC the SDRAM are burst oriented accesses start at a CAS 18 69 NC RAS 19 68 CLK selected location and continue for a programmed CS 20 67 CKE number of locations in a programmed sequence. A11 21 66 A9 Accesses begin with the registration of a BS0 22 65 A8 BS1 23 64 A7 BankActivate command which is then followed by a A10/AP 24 63 A6 Read or Write command. A0 25 62 A5 A1 26 61 A4 The AS4C4M32S provides for programmable A2 27 60 A3 Read or Write burst lengths of 1, 2, 4, 8, or full page, DQM2 28 59 DQM3 VDD 29 58 VSS with a burst termination option. An auto precharge NC 30 57 NC function may be enabled to provide a self-timed row DQ16 31 56 DQ31 precharge that is initiated at the end of the burst VSSQ 32 55 VDDQ DQ17 33 54 DQ30 sequence. The refresh functions, either Auto or Self DQ18 34 53 DQ29 Refresh are easy to use. VDDQ 35 52 VSSQ DQ19 36 51 DQ28 By having a programmable mode register, the DQ20 37 50 DQ27 system can choose the most suitable modes to VSSQ 38 49 VDDQ DQ21 39 48 DQ26 maximize its performance. These devices are well DQ22 40 47 DQ25 suited for applications requiring high memory VDDQ 41 46 VSSQ bandwidth. DQ23 42 45 DQ24 VDD 43 44 VSS Alliance Memory, Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory, Inc. reserves the right to change products or specification without notice. AS4C4M32S Figure 2. Block Diagram 4096 x 256 x 32 CLOCK CLK CELL ARRAY BUFFER (BANK 0) Column Decoder CKE CS DQ0 RAS DQ Buffer COMMAND DQ31 CAS DECODER CONTROL WE SIGNAL GENERATOR DQM0~3 4096 x 256 x 32 CELL ARRAY COLUMN (BANK 1) A10/AP COUNTER Column Decoder MODE REGISTER A0 ADDRESS BUFFER 4096 x256 x 32 A9 CELL ARRAY A11 (BANK 2) BA0 Column Decoder REFRESH BA1 COUNTER 4096 x 256 x 32 CELL ARRAY (BANK 3) Column Decoder Alliance Memory, Inc. Confidential 2 Rev.3.0 May. /2014 ~ Row Row Row Row Decoder Decoder Decoder Decoder ~