Product Information

P1010NSN5HFB

P1010NSN5HFB electronic component of NXP

Datasheet
NXP Freescale Microprocessors - MPU 32-Bit 800 MHz Trusted Boot Rev 1

Manufacturer: NXP
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - Global Stock

MOQ : 8
Multiples : 8
8 : USD 58.823
N/A

Obsolete
0 - Global Stock

MOQ : 1
Multiples : 1
1 : USD 59.7447
5 : USD 59.1337
10 : USD 58.533
25 : USD 57.9427
N/A

Obsolete
     
Manufacturer
Product Category
Core
Data Bus Width
Maximum Clock Frequency
Interface Type
Operating Supply Voltage
Number of Cores
Mounting Style
Package / Case
L1 Cache Instruction Memory
L1 Cache Data Memory
Minimum Operating Temperature
Maximum Operating Temperature
Packaging
Memory Type
Brand
Number Of I/Os
I/O Voltage
Instruction Type
L2 Cache Instruction / Data Memory
Number Of Timers/Counters
Processor Series
Watchdog Timers
Cnhts
Hts Code
Mxhts
Factory Pack Quantity :
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Freescale Semiconductor Document Number: P1010EC Data Sheet: Advance Information Rev. 4, 05/2014 P1010 P1010 QorIQ Integrated Processor Hardware TePBGA1-425 19 mm x 19 mm Specifications The following list provides an overview of the P1010 feature DDR3/DDR3L SDRAM memory controller supports set: 32-bit without ECC and 16-bit with ECC Programmable interrupt controller (PIC) compliant with High-performance 32-bit Book E-enhanced core based on OpenPIC standard the Power Architecture technology: One 4-channel DMA controller 36-bit physical addressing 2 Two I C interfaces Double-precision floating-point support Four UART interfaces 32-Kbyte L1 instruction cache and 32-Kbyte L1 data Two FlexCAN (version 2.0b) interfaces cache Integrated Flash controller (IFC) 400- to 1000-MHz clock frequency TDM 256-Kbyte L2 cache with ECC. Also configurable as 16 general-purpose I/O signals SRAM and stashing memory Operating temperature (Ta - T ) range: 0105 C (standard) Secure boot capability j and 40 C to 105 C (extended) Three enhanced three-speed Ethernet controllers (eTSECs) 19 19 mm 425-ball wirebond TePBGA-1 package with 10/100/1000 Mbps support 0.8 mm pitch TCP/IP acceleration, quality of service, and classification capabilities IEEE Std 1588 support RGMII, SGMII eTSEC1 supports both RGMII/SGMII interfaces and eTSEC2, eTSEC3 support SGMII interface High-speed interfaces supporting the following multiplexing options: Two PCI Express 1.1 interfaces Two SATA Revision 2.0 interfaces Six lanes of high-speed serial interfaces to be shared between PCI Express, SATA, and SGMII High-speed USB controller (USB 2.0) Host and device support On-chip USB 2.0 high-speed PHY Enhanced host controller interface (EHCI) ULPI interface Enhanced secure digital host controller (SD/MMC) Enhanced serial peripheral interface (eSPI) Integrated security engine (ULE CAAM) Protocol support includes DES, AES, RNG, CRC, MDE, PKE, SHA, and MD5. This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2011-2014. All rights reserved.Table of Contents 1 Pin assignments and reset states .4 2.22 PCI Express . 80 1.1 Ball layout diagrams 4 2.23 Serial ATA (SATA) 84 1.2 Pinout assignments 11 3 Hardware design considerations 88 2 Electrical characteristics .22 3.1 System clocking 88 2.1 Overall DC electrical characteristics .22 3.2 Supply power default setting 91 2.2 Power sequencing .26 3.3 Power supply design and sequencing . 92 2.3 Power-down Requirements 27 3.4 Decoupling recommendations . 93 2.4 Reset Initialization .27 3.5 SerDes block power supply decoupling 2.5 Power-on ramp rate 28 recommendations 93 2.6 Power characteristics 29 3.6 Connection recommendations . 93 2.7 Input clocks 31 3.7 Pull-up and pull-down resistor requirements 93 2.8 DDR3, and DDR3L SDRAM controller .33 3.8 Output buffer DC impedance . 94 2.9 eSPI .41 3.9 Configuration pin muxing . 94 2.10 DUART .42 3.10 JTAG configuration signals . 95 2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) .43 3.11 Guidelines for high-speed interface termination . 97 2.12 USB 54 3.12 Thermal 98 2.13 Integrated flash controller .58 4 Package information 100 2.14 Enhanced secure digital host controller (eSDHC) 62 4.1 Package parameters for P1010 . 100 2.15 Programmable Interrupt Controller (PIC) 4.2 Mechanical dimensions of P1010 WB-TePBGA 100 specifications 64 5 Security fuse processor 101 2.16 JTAG .65 6 Ordering information 102 2 2.17 I C .67 6.1 Part marking . 102 2.18 GPIO .69 7 Product documentation 102 2.19 FlexCAN 71 8 Revision history 103 2.20 TDM .72 2.21 High-Speed Serial Interfaces (HSSI) 74 P1010 QorIQ Integrated Processor Hardware Specifications, Rev. 4 2 Freescale Semiconductor

Tariff Desc

8542.31.00 52 No ..CMOS and MOS Microprocessors (MPU), Microcontrollers (MCU) and Digital Signal Processors (DSP)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits Digital.
FR9
Freescale
FREESCALE SEMI
Freescale Semicon
FREESCALE SEMICONDUC
Freescale Semiconductor
Freescale Semiconductor - NXP
NXP
NXP Freescale
NXP (FREESCALE)
NXP / Freescale
NXP SEMI
NXP Semicon
NXP SEMICONDUCTOR
NXP Semiconductors
NXP USA Inc.
PH3
PHI

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